DS1977 datasheet(3/29 Pages) MAXIM

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DS1977

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PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Standard speed, VPUP > 4.5V

(Note 1)

Standard speed (Note 1)

Presence Detect

Sample Time

tMSP

Overdrive speed (Note 1)

7.5

10.5

µs

I/O Pin, 1-Wire Write

Standard speed (Notes 1, 13)

120

Write-0 Low Time

tW0L

Overdrive speed (Notes 1, 13)

µs

Standard speed (Notes 1, 13)

Write-1 Low Time

tW1L

Overdrive speed (Notes 1, 13)

µs

I/O Pin, 1-Wire Read

Standard speed (Notes 1, 14)

15 -



Read Low Time

tRL

Overdrive speed (Notes 1, 14)

2 -



µs

Standard speed,

VPUP > 4.5V (Notes 1, 14)

tRL + 

Standard speed (Notes 1, 14)

tRL + 

Read Sample Time

tMSR

Overdrive speed (Notes 1, 14)

tRL + 

µs

I/O Pin, Strong Pullup

Strong Pullup Read

tSPUR

(Note 1)

2.64

Strong Pullup Write

tSPUW

(Note 1)

22.46

Strong Pullup password

verification

tSPUV

(Note 1)

0.62

EEPROM

Programming Current

ILPROG

Write/Erase Cycles

NCYCLE

100k

—

Data Retention

tRET

years

Note 1:

System requirement.

Note 2:

Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The

specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded

systems, an active pullup such as that found in the DS2480B may be required.

Note 3:

Capacitance on the data pin could be 5nF when power is first applied.

Note 4:

VTL and VTH are functions of the internal supply voltage, which is a function of VPUP and the 1-Wire recovery times. The VTH and VTL

maximum specifications are valid at VPUPMAX (5.25V). In any case, VTL < VTH < VPUP.

Note 5:

Voltage below which, during a falling edge on I/O, a logic '0' is detected.

Note 6:

The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low.

Note 7:

Voltage above which, during a rising edge on I/O, a logic '1' is detected.

Note 8:

After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be detected as logic '0'.

Note 9:

The I-V characteristic is linear for voltages less than 1V.

Note 10:

The earliest recognition of a negative edge is possible at tREH after VTH has been reached before.

Note 11:

Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.

Note 12:

Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 90%

of VPUP and the time at which the voltage is 10% of VPUP.

Note 13:

 in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual maximum

duration for the master to pull the line low is tW1LMAX + tF -  and tW0LMAX + tF -  respectively.

Note 14:

 in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input-high threshold of

the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.

Standard Values

DS1977 Values

Standard Speed

Overdrive Speed

Standard Speed

Overdrive Speed

Parameter

Name

min

max

min

max

min

max

min

max

tSLOT (incl. tREC)

61µs

(undef.)

7µs

(undef.)

65µs

(undef.)

8µs

(undef.)

tRSTL

480µs

(undef.)

48µs

80µs

480µs

640µs

48µs

80µs

tPDH

15µs

60µs

2µs

6µs

15µs

60µs

2.5µs

6.5µs

tPDL

60µs

240µs

8µs

24µs

60µs

240µs

8µs

24µs

tW0L

60µs

120µs

6µs

16µs

60µs

120µs

6µs

16µs

1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.

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