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MAXQ3181-RAN+ Datasheet(PDF) 39 Page - Maxim Integrated Products |
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MAXQ3181-RAN+ Datasheet(HTML) 39 Page - Maxim Integrated Products |
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39 / 84 page ![]() Low-Power, Active Energy, Polyphase AFE ______________________________________________________________________________________ 39 Interrupt Mask, Phase X = A/B/C (X.MASK) (A: 0x145, B: 0x231, C: 0x31D) Energy Overflow Flags, Phase X = A/B/C (X.EOVER) (A: 0x146, B: 0x232, C: 0x31E) These bits indicate that an overflow condition has occurred on an energy accumulator. An overflow condition is not an error condition. Rather, it simply indicates that the value in the energy accumulator could be smaller than the pre- vious reading due to the overflow in the counter. To obtain the actual energy usage since the previous reading, 0x100000000 must be added to the difference. These bits, once set, can be cleared only by the host. Bit: 7 6 5 4 3 2 1 0 Name: — DIR_A — DCHAM NOZXM UVM OVM OCM Reset: 0 0 0 0 0 0 0 0 BIT NAME FUNCTION 7, 5 — Reserved. 6 DIR_A Active Energy Direction Status 0 = positive 1 = negative 4 DCHAM Real Energy Direction Change Mask. If set, a change in real power direction on phase X causes the DCHA flag in the IRQ_FLAG register to be set. 3 NOZXM No-Zero Crossing Mask. If set, a no-zero crossing on phase X causes the NOZX flag in the IRQ_FLAG register to be set. 2 UVM Undervoltage Mask. If set, an undervoltage condition on phase X causes the UV flag in the IRQ_FLAG register to be set. 1 OVM Overvoltage Mask. If set, an overvoltage condition on phase X causes the OV flag in the IRQ_FLAG register to be set. 0 OCM Overcurrent Mask. If set, an overcurrent condition on phase X causes the OC flag in the IRQ_FLAG register to be set. BIT NAME FUNCTION 7:5, 3:2 — Reserved. 4 SOV When set, indicates an overflow condition on the apparent energy accumulator. 1 ANOV When set, indicates an overflow condition on the real negative energy accumulator. 0 APOV When set, indicates an overflow condition on the real positive energy accumulator. Bit: 7 6 5 4 3 2 1 0 Name: — — — SOV — — ANOV APOV Reset: 0 0 0 0 0 0 0 0 |
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