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APL5930KAI Datasheet(PDF) 12 Page - Anpec Electronics Coropration

Part # APL5930KAI
Description  3A, Ultra Low Dropout (0.23V Typical) Linear Regulator
PDF  17 Pages
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Manufacturer  ANPEC [Anpec Electronics Coropration]
Direct Link  http://www.anpec.com.tw
Logo ANPEC - Anpec Electronics Coropration

APL5930KAI Datasheet(HTML) 12 Page - Anpec Electronics Coropration

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Copyright
© ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
APL5930
www.anpec.com.tw
12
Layout Consideration
Figure 2
Thermal Consideration
1.
Please solder the Exposed Pad on the VIN pad on
the top-layer of PCBs. The VIN pad must have wide
size to conduct heat into the ambient air through the
VIN plane and PCB as a heat sink.
2.
Please place the input capacitors for VIN and VCNTL
pins near the pins as close as possible for
decoupling high-frequency ripples.
3.
Ceramic decoupling capacitors for load must be
placed near the load as close as possible for
decoupling high-frequency ripples.
4.
To place APL5930 and output capacitors near the
load reduces parasitic resistance and inductance
for excellent load transient response.
5.
The negative pins of the input and output capacitors
and the GND pin must be connected to the ground
plane of the load.
6.
Large current paths, shown by bold lines on the fig-
ure 1, must have wide tracks.
7.
Place the R1, R2, and C1 near the APL5930 as close
as possible to avoid noise coupling.
8.
Connect the ground of the R2 to the GND pin by us-
ing a dedicated track.
9.
Connect the one pin of the R1 to the load for Kelvin
sensing.
10. Connect one pin of the C1 to the VOUT pin for reli-
able feedback compensation.
Refer to the figure 2, the SOP-8P is a cost-effective pack-
age featuring a small size like a standard SOP-8 and a
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current applica-
tions. The exposed pad must be soldered to the top-layer
VIN plane. The copper of the VIN plane on the Top layer
conducts heat into the PCB and ambient air. Please en-
large the area of the top-layer pad and the VIN plane to
reduce the case-to-ambient resistance (
θ
CA).
V
CNTL
V
OUT
C
CNTL
V
IN
GND
VOUT
VCNTL
VIN
C
IN
C
OUT
APL5930
R1
C1
FB
R2
Load
Figure 1
Exposed
Pad
Die
Top
VIN
plane
PCB
Ambient
Air
118 mil
102 mil
SOP-8P
5
6
7
8
1
2
3
4
Top
VOUT
plane
Recommended Minimum Footprint
0.050
0.024
1
2
3
4
8
7
6
5
0.138
Unit : Inch



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