HT48F70E datasheet(32/58 Pages) HOLTEK

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HT48F70E

Rev. 1.30

July 29, 2009

Interrupts

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer/Event Counter requires microcontroller

attention, their corresponding interrupt will enforce a

temporary suspension of the main program allowing the

microcontroller to direct attention to their respective

needs. The device contains a single external interrupt

and two internal timer interrupt functions. The external

interrupt is controlled by the action of the external INT

pin, while the internal interrupts are controlled by the

Timer/Event Counters overflow.

Interrupt Register

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by a single INTC

controlling the appropriate enable bits in this register

each individual interrupt can be enabled or disabled.

Also when an interrupt occurs, the corresponding re-

quest flag will be set by the microcontroller. The global

enable flag if cleared to zero will disable all interrupts.

Interrupt Operation

A Timer/Event Counter overflow or the external interrupt

line being pulled low will all generate an interrupt re-

quest by setting their corresponding request flag, if their

appropriate interrupt enable bit is set. When this hap-

pens, the Program Counter, which stores the address of

the next instruction to be executed, will be transferred

onto the stack. The Program Counter will then be loaded

with a new address which will be the value of the corre-

sponding interrupt vector. The microcontroller will then

fetch its next instruction from this interrupt vector. The

instruction at this vector will usually be a JMP statement

which will take program execution to another section of

program which is known as the interrupt service routine.

Here is located the code to control the appropriate inter-

rupt. The interrupt service routine must be terminated

with a RETI statement, which retrieves the original Pro-

gram Counter address from the stack and allows the

microcontroller to continue with normal execution at the

point where the interrupt occurred.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the following dia-

gram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

I N T C R e g i s t e r

M a s t e r I n t e r r u p t G l o b a l E n a b l e

1 : g l o b a l e n a b l e

0 : g l o b a l d i s a b l e

N o i m p l e m e n t e d , r e a d a s " 0 "

b 7

b 0

E T 0 I E E I

E M I

T i m e r / E v e n t C o u n t e r 0 I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 0 I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

E I F

T 0 F

E x t e r n a l I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

E x t e r n a l I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

T 1 F

E T 1 I

T i m e r / E v e n t C o u n t e r 1 I n t e r r u p t R e q u e s t F l a g

1 : a c t i v e

0 : i n a c t i v e

T i m e r / E v e n t C o u n t e r 1 I n t e r r u p t E n a b l e

1 : e n a b l e

0 : d i s a b l e

Interrupt Control Register

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