HT56R656 datasheet(46/108 Pages) HOLTEK

46 / 108 page

HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

Rev. 1.00

July 20, 2009

high, the counter will increment each time the external

timer pin receives a high to low transition. When it is full

and overflows, an interrupt signal is generated and the

Timer/Event Counter will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the

Timer/Event Counter Interrupt Enable bit in the

corresponding Interrupt Control Register, is reset to

zero.

As the external timer pin is shared with an I/O pin, to en-

sure that the pin is configured to operate as an event

counter input pin, two things have to happen. The first is

to ensure that the Operating Mode Select bits in the

Timer Control Register place the Timer/Event Counter in

the Event Counting Mode, the second is to ensure that

the port control register configures the pin as an input. It

should be noted that in the event counting mode, even if

the microcontroller is in the Power Down Mode, the

Timer/Event Counter will continue to record externally

changing logic events on the timer input pin. As a result

when the timer overflows it will generate a timer interrupt

and corresponding wake-up source.

Configuring the Pulse Width Measurement Mode

In this mode, the Timer/Event Counter can be utilised to

measure the width of external pulses applied to the ex-

ternal timer pin. To operate in this mode, the Operating

Mode Select bit pair, TnM1/TnM0, in the Timer Control

Control Register Operating Mode

Select Bits for the Pulse Width

Measurement Mode

Bit7 Bit6

In this mode the internal clock, fSYS, is used as the inter-

nal clock for the 8-bit Timer/Event Counter and fSUB or

fSYS/4 is used as the internal clock for the 16-bit

Timer/Event Counter. However, the clock source, fSYS,

for the 8-bit timer is further divided by a prescaler, the

value of which is determined by the Prescaler Rate Se-

lect bits TnPSC2~TnPSC0, which are bits 2~0 in the

Timer Control Register. After the other bits in the Timer

Control Register have been setup, the enable bit TnON,

which is bit 4 of the Timer Control Register, can be set

high to enable the Timer/Event Counter, however it will

not actually start counting until an active edge is re-

ceived on the external timer pin.

If the Active Edge Select bit TnE, which is bit 3 of the

Timer Control Register, is low, once a high to low transi-

tion has been received on the external timer pin, the

Timer/Event Counter will start counting until the external

timer pin returns to its original high level. At this point the

enable bit will be automatically reset to zero and the

Timer/Event Counter will stop counting. If the Active

Edge Select bit is high, the Timer/Event Counter will be-

gin counting once a low to high transition has been re-

ceived on the external timer pin and stop counting when

the external timer pin returns to its original low level. As

before, the enable bit will be automatically reset to zero

and the Timer/Event Counter will stop counting. It is im-

portant to note that in the Pulse Width Measurement

Mode, the enable bit is automatically reset to zero when

the external control signal on the external timer pin re-

turns to its original level, whereas in the other two

modes the enable bit can only be reset to zero under

program control.

The residual value in the Timer/Event Counter, which

can now be read by the program, therefore represents

the length of the pulse received on the external timer

pin. As the enable bit has now been reset, any further

transitions on the external timer pin will be ignored. Not

until the enable bit is again set high by the program can

the timer begin further pulse width measurements. In

this way, single shot pulse measurements can be easily

Made.

It should be noted that in this mode the Timer/Event

Counter is controlled by logical transitions on the exter-

nal timer pin and not by the logic level. When the

T i m e r + 2

E x t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3

T i m e r + 1

Event Counter Mode Timing Chart

+ 1

+ 2

+ 3

+ 4

T i m e r

E x t e r n a l T M R

P i n I n p u t

T n O N - w i t h T n E = 0

P r e s c a l e r O u t p u t

I n c r e m e n t

T i m e r C o u n t e r

Pulse Width Measure Mode Timing Chart

HT56R656 Datasheet(PDF) 46 Page - Holtek Semiconductor Inc

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