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HT56R656 Datasheet(PDF) 72 Page - Holtek Semiconductor Inc |
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HT56R656 Datasheet(HTML) 72 Page - Holtek Semiconductor Inc |
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72 / 108 page ![]() HT56R62/HT56R65 HT56R642/HT56R644/HT56R654/HT56R656 Rev. 1.00 72 July 20, 2009 A u t o m a t i c a l l y C l e a r e d b y I S R e x c e p t f o r A D F , T B F , R T F a n d T 2 F M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e A u t o m a t i c a l l y D i s a b l e d b y I S R C a n b e E n a b l e d M a n u a l l y P r i o r i t y H i g h I n t e r r u p t P o l l i n g E x t e r n a l I n t e r r u p t R e q u e s t F l a g E I F 1 E E I 0 T i m e r / E v e n t C o u n t e r 0 I n t e r r u p t R e q u e s t F l a g T 0 F E E I 1 E T 0 I T i m e r / E v e n t C o u n t e r 1 I n t e r r u p t R e q u e s t F l a g T 1 F E T 1 I S P I / I 2 C I n t e r r u p t R e q u e s t F l a g S I M F E S I M E x t e r n a l I n t e r r u p t R e q u e s t F l a g E I F 0 M u l t i - f u n c t i o n I n t e r r u p t R e q u e s t F l a g M F F E M F I E M I L o w T i m e B a s e I n t e r r u p t R e q u e s t F l a g T B F E A D I R e a l T i m e C l o c k I n t e r r u p t R e q u e s t F l a g R T F E R T I A / D C o n v e r t e r I n t e r r u p t R e q u e s t F l a g A D F E T B I E P I E x t e r n a l P e r i p h e r a l I n t e r r u p t R e q u e s t F l a g P E F T i m e r / E v e n t C o u n t e r 2 I n t e r r u p t R e q u e s t F l a g T 2 F E T 2 I N o t e t h a t n o t a l l d e v i c e s c o n t a i n T i m e r / E v e n t C o u n t e r 2 . Interrupt Structure interrupt vector at location 04H or 08H, will take place. When the interrupt is serviced, the external interrupt request flags, EIF0 or EIF1, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on this pin will remain valid even if the pin is used as an external interrupt input. The INTEDGE register is used to select the type of active edge that will trigger the external interrupt. A choice of ei- ther rising and falling edge types can be chosen along with an option to allow both edge types to trigger an exter- nal interrupt. Note that the INTEDGE register can also be used to disable the external interrupt function. The external interrupt pins are connected to an internal filter to reduce the possibility of unwanted external inter- rupts due to adverse noise or spikes on the external in- terrupt input signal. As this internal filter circuit will consume a limited amount of power, a configuration op- tion is provided to switch off the filter function, an option which may be beneficial in power sensitive applications, but in which the integrity of the input signal is high. Care must be taken when using the filter on/off configuration option as it will be applied not only to both the external interrupt pins but also to the Timer/Event Counter exter- nal input pins. Individual external interrupt or Timer/Event Counter pins cannot be selected to have a filter on/off function. External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function interrupt. For an external peripheral interrupt to occur, the global interrupt enable bit, EMI, external peripheral interrupt enable bit, EPI, and Multi-function interrupt enable bit, EMFI, must first be set. An actual external peripheral in- terrupt will take place when the external interrupt re- quest flag, PEF, is set, a situation that will occur when a negative transition, appears on the PINT pin. The exter- F i l t e r O n / O f f C o n f i g u r a t i o n O p t i o n I N T C 1 F i l t e r I N T C 0 F i l t e r E x t e r n a l I N T . 0 E x t e r n a l I N T . 1 M C U |
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