HT82B40R datasheet(22/57 Pages) HOLTEK

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HT82B40R/HT82B40A

Rev. 1.10

September 4, 2009

I N T C R e g i s t e r

M a s t e r i n t e r r u p t g l o b a l e n a b l e

1 : g l o b a l e n a b l e

0 : g l o b a l d i s a b l e

U S B i n t e r r u p t e n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 0 i n t e r r u p t e n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 1 i n t e r r u p t e n a b l e

1 : e n a b l e

0 : d i s a b l e

U S B i n t e r r u p t r e q u e s t f l a g

1 : a c t i v e

0 : i n a c t i v e

T i m e r / E v e n t C o u n t e r 0 i n t e r r u p t r e q u e s t f l a g

1 : a c t i v e

0 : i n a c t i v e

T i m e r / E v e n t C o u n t e r 1 i n t e r r u p t r e q u e s t f l a g

1 : a c t i v e

0 : i n a c t i v e

F o r t e s t m o d e u s e d o n l y

M u s t b e w r i t t e n a s " 0 " ; o t h e r w i s e m a y r e s u l t i n u n p r e d i c t a b l e o p e r a t i o n

b 7

b 0

E T 0 I

E U I

E M I

U S B F

T 0 F

E T 1 I

T 1 F

INTC Register

A u t o m a t i c a l l y C l e a r e d b y I S R

M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e

U S B I n t e r r u p t

R e q u e s t F l a g U S B F

E M I

P r i o r i t y

I n t e r r u p t

P o l l i n g

H i g h

A u t o m a t i c a l l y D i s a b l e d b y I S R

C a n b e E n a b l e d M a n u a l l y

T i m e r / E v e n t C o u n t e r 0 O v e r f l o w

I n t e r r u p t R e q u e s t F l a g T 0 F

E T 0 I

L o w

T i m e r / E v e n t C o u n t e r 1 O v e r f l o w

I n t e r r u p t R e q u e s t F l a g T 1 F

E T 1 I

F I F O

Interrupt Structure

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

USB Interrupt

0004H

Timer/Event Counter 0 Overflow

Interrupt

0008H

Timer/Event Counter 1 Overflow

Interrupt

000CH

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the interrupt

registers can prevent simultaneous occurrences.

Timer/Event Counter Interrupt

For a Timer/Event Counter interrupt to occur, the global

interrupt enable bit, EMI, and the corresponding timer

interrupt enable bit, ET0I/ET1I, must first be set. An ac-

tual Timer/Event Counter interrupt will take place when

the Timer/Event Counter interrupt request flag,

T0F/T1F, is set, a situation that will occur when the

Timer/Event Counter overflows. When the interrupt is

enabled, the stack is not full and a Timer/Event Counter

overflow occurs, a subroutine call to the timer interrupt

vector at location 08H/0CH, will take place. When the in-

terrupt is serviced, the timer interrupt request flag,

T0F/T1F, will be automatically reset and the EMI bit will

be automatically cleared to disable other interrupts.

HT82B40R Datasheet(PDF) 22 Page - Holtek Semiconductor Inc

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