HT82K74E datasheet(15/56 Pages) HOLTEK

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HT82K74E/HT82K74EE

Rev. 1.00

December 15, 2009

In addition, on entering an interrupt sequence or execut-

ing a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status registers are important and if the interrupt rou-

tine can change the status register, precautions must be

taken to correctly save it.

Interrupt Control Registers

- INTC

The microcontroller provides an internal timer/event

counter overflow interrupt. By setting various bits within

this register using standard bit manipulation instruc-

tions, the enable/disable function of each interrupt can

be independently controlled. A master interrupt bit within

this register, the EMI bit, acts like a global enable/dis-

able and is used to set all of the interrupt enable bits on

or off. This bit is cleared when an interrupt routine is en-

tered to disable further interrupt and is set by executing

the

²RETI² instruction.

Timer/Event Counter Registers

TMRH, TMRL, TMRC

All devices possess a single internal 16-bit count-up

timer. An associated register pair known as

TMRL/TMRH is the location where the timer 16-bit value

is located. This register can also be preloaded with fixed

data to allow different time intervals to be setup. An as-

sociated control register, known as TMRC, contains the

setup information for this timer, which determines in

what mode the timer is to be used as well as containing

the timer on/off control function.

Watchdog Timer Register

- WDTS

The Watchdog function in the microcontroller provides

an automatic reset function giving the microcontroller a

means of protection against spurious jumps to incorrect

Program Memory addresses. To implement this, a timer

is provided within the microcontroller which will issue a

reset command when its value overflows.To provide

variable Watchdog Timer reset times, the Watchdog

Timer clock source can be divided by various division ra-

tios, the value of which is set using the WDTS register.

By writing directly to this register, the appropriate divi-

sion ratio for the Watchdog Timer clock source can be

setup. Note that only the lower 3 bits are used to set divi-

sion ratios between 1 and 128.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O

registers and their associated control registers play a

prominent role. All I/O ports have a designated register

correspondingly labeled as PA, PB, PC, PD and PE.

These labeled I/O registers are mapped to specific ad-

dresses within the Data Memory as shown in the Data

Memory table, which are used to transfer the appropri-

ate output or input data on that port. With each I/O port

there is an associated control register labeled PAC,

PBC, PCC, PDC, PEC also mapped to specific ad-

dresses with the Data Memory. The control register

specifies which pins of that port are set as inputs and

which are set as outputs. To setup a pin as an input, the

corresponding bit of the control register must be set

high, for an output it must be set low. During program , it

is important to first setup the control registers to specify

which pins are outputs and which are inputs before

reading data from or writing data to the I/O ports. One

flexible feature of these registers is the ability to directly

program single bits using the

²SET [m].i² and ²CLR

[m].i

² instructions. The ability to change I/O pins from

output to input and vice versa by manipulating specific

bits of the I/O control registers during normal program

operation is a useful feature of these devices.

EEPROM Data Memory

An area of EEPROM, which stands for Electrically Eras-

able Programmable Read Only Memory, is contained

within the device. This type of memory is non-volatile

with data retention even after power is removed. This

type of memory is useful for storing information such as

product identification numbers, calibration values, user

data, system setup data etc.

EEPROM Memory Structure

The EEPROM has a capacity is 128 organised into a

structure of 8-bit words. The EEPROM is an IIC type de-

vice and therefore operates using a two wire serial bus.

Accessing the EEPROM Data Memory

The two IIC lines are the Serial Clock line, SCL, and the

Serial Data line SDA. The SDA pin is shared with I/O pin

PE0, while the SCL pin is connected to internal I/O PE1.

Normal I/O control software instructions for PE0 and

PE1 are used to control read and write operations on the

EEPROM.

· Serial data - SDA

The SDA line is the bidirectional EEPROM serial data

line which is shared with pin PE0.

If it is transfer data must be output mode, and it re-

ceive data should be set input mode and select pull

high resistor by option.

· Serial data - SCL

The SCL line is the EEPROM serial clock input line

which is shared with internal I/O PE1. The SCL input

clocks data into the EEROM on its positive edge and

clocks data out of the EEPROM on its negative edge.

· Clock and data transition

Data transfer may be initiated only when the bus is not

busy. During data transfer, the data line must remain

stable whenever the clock line is high. Changes in the

data line while the clock line is high will be interpreted

as a START or STOP condition.

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