HT82K74E datasheet(30/56 Pages) HOLTEK

30 / 56 page

HT82K74E/HT82K74EE

Rev. 1.00

December 15, 2009

Wake-up

After the system enters the Power Down Mode, it can be

woken up from one of various sources listed as follows:

· An external reset

· An external falling or rising edge on any of the I/O pins

· A system interrupt

· A WDT overflow (if the contents of the PTR are zeros)

· A PTR overflow occurs (if the contents of the PTR are

not equal to zeros)

If the system is woken up by an external reset, the de-

vice will experience a full system reset, however, if the

device is woken up by a WDT overflow, a Watchdog

Timer reset will be initiated. Although both of these

wake-up methods will initiate a reset operation, the ac-

tual source of the wake-up can be determined by exam-

ining the TO and PDF flags. The PDF flag is cleared by a

system power-up or executing the clear Watchdog

Timer instructions and is set when executing the

²HALT²

instruction. The TO flag is set if a WDT time-out occurs,

and causes a wake-up that only resets the Program

Counter and Stack Pointer, the other flags remain in

their original status. Note that the WDT time-out will not

occur if the contents of the Period Timer Register (PTR)

are not equal to zeros.

Each pin on Port A or any nibble on other ports can be

setup via configuration options to permit a negative or

positive transition on the pin to wake-up the system.

When a port pin wake-up occurs, the program will re-

sume execution at the instruction following the

²HALT²

instruction.

If the system is woken up by an interrupt, then two possi-

ble situations may occur. The first is where the interrupt

is disabled or the interrupt is enabled but the stack is full,

in which case the program will resume execution at the

instruction following the

²HALT² instruction. In this situa-

tion, the interrupt will not be immediately serviced, but

will rather be serviced later when the related interrupt is

finally enabled or when a stack level becomes free. The

other situation is where the related interrupt is enabled

and the stack is not full, in which case the regular inter-

rupt response takes place. If an interrupt request flag is

set to

²1² before entering the Power Down Mode, the

wake-up function of the related interrupt will be disabled.

No matter what the source of the wake-up event is, once

a wake-up situation occurs, a time period equal to 512

system clock periods will be required before normal sys-

tem operation resumes. However, if the wake-up has

originated due to an interrupt, the actual interrupt sub-

routine execution will be delayed by additional one or

more cycles. If the wake-up results in the execution of

the next instruction following the

²HALT² instruction, this

will be executed immediately after the 512 system clock

period delay has ended.

Watchdog Timer

The Watchdog Timer is provided to prevent program

malfunctions or sequences from jumping to unknown lo-

cations, due to certain uncontrollable external events

such as electrical noise. It operates by providing a de-

vice reset when the WDT counter overflows. The WDT

clock is supplied by its own internal dedicated internal

WDT oscillator. Note that if the WDT configuration op-

tion has been disabled, then any instruction relating to

its operation will result in no operation.

The WDT function is selected by a configuration option.

There is also an internal register associated with the

WDT named WDTS to select various WDT time-out pe-

riods in the device. The clock source of the WDT comes

from the internal WDT oscillator and its clock period may

vary with VDD, temperature and process variation. The

WDT clock is further divided by an internal 6-stage

counter followed by a 7-stage prescaler to obtain longer

WDT time-out period selected by the WDT prescaler

rate selection bits, WS2~WS0, in the associated WDT

There is only one instruction to clear the Watchdog

Timer known as

²CLR WDT². As the instruction ²CLR

WDT

² is executed, all contents of the 6-stage counter

and 7-stage prescaler will be clear. It makes the WDT

time-out period more accurate relatively.

Under normal program operation, a WDT time-out will

initialise a device reset and set the status bit TO. How-

ever, if the system is in the Power Down Mode, when a

WDT time-out occurs, the TO bit in the status register

will be set and only the Program Counter and Stack

Pointer will be reset. Three methods can be adopted to

clear the contents of the WDT. The first is an external

hardware reset, which means a low level on the RES

pin, the second is using the watchdog software instruc-

tions and the third is via a HALT instruction.

Although the WDT overflow is a source to wake up the

MCU from the Power Down Mode, there are some limi-

tations on the conditions at which the WDT overflow oc-

curs. If the WDT function is enabled and the PTR

contents are equal to zeros, the WDT overflow will occur

to wake up the MCU from the Power Down Mode. If the

PTR contents are not equal to zeros, the WDT overflow

will not occur in Power Down Mode even if the WDT

function has been enabled.

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