AS2702 – AS-Interface Slave IC

Revision 1.3, 21-Aug-08

Page 11 of 13

A ‘hard’ reset event conditions the slave device as follows:

•

Internal states (counters, flags, …) are reset

•

The slave device’s receiver is desynchronized from the AS-Interface bus

•

The low-side open-drain output stages at ports D3, …, D0 and ports P3, …, P0 are switched off

•

Any test mode will be cancelled

A ‘soft’ reset has the following consequences:

•

A regular, nominal 6µs L-phase strobe is generated on both the DSTBn and PSTBn pin

•

The low-side open-drain output stages at ports D3, …, D0 and ports P3, …, P0 are switched off

•

Internal states (counters, flags, …) are rest, however the following states and operations are not affected:

– the timer function which controls blinking of LED1 and LED2

– the data communication

– any test mode

– any EEPROM write operation

Remark:

If UOUT drops below VCOMOFF = nom. 10V data communication with the AS-Interface bus is aborted by the receiver or transmitter

of the slave device. As long as U5R does not drop below 3.75V in this situation, no ‘hard’ reset takes place; however the data

communication watchdog will be triggered (unless disabled) and a ‘soft’ reset will result.

EEPROM

AS2702 has a 16 x 8 Bits serial interface EEPROM on board to store the slave unit’s address and set-up data in a non-volatile

fashion.

The EEPROM stores the following data:

EEPROM-Address

Data

Relevant No. of Bits

Programmed by

Note

0, 1

Slave Address

5 + 1

Master (Initialization)

1

2

Settings (EID1)

4

Master (Initialization)

3

Settings (IO-Conf.)

5

Slave unit manufacturer

4

Settings (ID)

5

Slave unit manufacturer

5

Settings (EID2)

5

Slave unit manufacturer

6

Settings (Control-Code)

5

Slave unit manufacturer

Note:

1

6 Bits (A4, …, A0 + Sel-bit) in extended address mode: 62 slaves addressable;

5 Bits (A4, …, A0) in non-extended address mode: 31 slaves addressable

Obviously the capacity of the EEPROM is only partially used.

Reading and writing of the EEPROM is performed bytewise and trough temporary, volatile registers.

Writing of data from the volatile register into the EEPROM takes about 10ms per byte, whereas reading takes less than 1ms per

byte.

Upon RESET the EEPROM info is read into temporary register, including the slave’s address which has been written redundantly

into EEPROM locations 0 and 1 before.

The temporary registers receiving the address are compared for similarity; in case of non-similarity – which e.g. may have been

caused by a supply voltage dip during address writing – the slave will flag non-regular operation status/slave address zero.