DM9008CEP datasheet(21/52 Pages) DAVICOM

21 / 52 page

DM9008C

Ethernet Controller with General Processor Interface

Preliminary

Version: DM9008C-13-DS-P01

January 15, 2008

6.24 Chip Revision Register (2CH)

Bit

Name

Default

Description

7:0

CHIPR

P,1AH,RO

CHIP Revision

6.25 Transmit Control Register 2 ( 2DH )

Bit

Name

Default

Description

LED

P0,RW

Led Mode

When set, the LED pins act as led mode 1.

When cleared, the led mode is default mode 0 or depending EEPROM setting.

RLCP

P0,RW

Retry Late Collision Packet

Re-transmit the packet with late-collision

DTU

P0,RW

Disable TX Under run Retry

Disable to re-transmit the underruned packet

ONEPM

P0,RW

One Packet Mode

When set, only one packet transmit command can be issued before transmit

completed.

When cleared, at most two packet transmit command can be issued before

transmit completed.

3~0

IFGS

P0,RW

Inter-Frame Gap Setting

0XXX: 96-bit

1000: 64-bit

1001: 72-bit

1010:80-bit

1011:88-bit

1100:96-bit

1101:104-bit

1110: 112-bit

1111:120-bit

6.26 Operation Test Control Register ( 2EH )

Bit

Name

Default

Description

7~6

SCC

P0,RW

System Clock Control

Set the internal system clock.

00: 50Mhz

01: 20MHz

10: 100MHz

11: Reserved

RESERVED

P0,RW

Reserved

SOE

P0,RW

Internal SRAM Output-Enable Always ON

SCS

P0,RW

Internal SRAM Chip-Select Always ON

2~0

PHYOP

P0,RW

Internal PHY operation mode for testing

6.27 Special Mode Control Register ( 2FH )

Bit

Name

Default

Description

SM_EN

P0,RW

Special Mode Enable

6~3

RESERVED

P0,RW

Reserved

FLC

P0,RW

Force Late Collision

FB1

P0,RW

Force Longest Back-off time

FB0

P0,RW

Force Shortest Back-off time

DM9008CEP Datasheet(PDF) 21 Page - Davicom Semiconductor, Inc.

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