07/03/01

5

ES5129

4-1/2 digit with LCD

10

A4, G4, D4

O Output to LCD segment.

11

F4, E4, DP4

O Output to LCD segment.

12

BP3

O LCD backplane signal

13

BP2

O LCD backplane signal

14

BP1

O LCD backplane signal

15

VDISP

P Negative supply for display drivers.

16

DP4/OR

I/O Input: Turns on most significant decimal point when HI.

Output: Pulled HI when result count exceeds ±19,999.

17

TEST2

O TEST pin. Not connect.

18

DP3/UR

Output: Pulled HI when result count is less than ±1,000.

19

LATCH/HOLD I/O Input: when floating, ES5129 operates in the free-run mode.

When pulled high, the last display reading is held. When

pulled LO, the result counter contents are shown

incrementing during the de-integrate phase of cycle.

Output: Negative going edge occurs when the data latches are

upgraded. Can be used as a converter status signal.

20

V-

P Negative power supply terminal

21

V+

P Positive power supply terminal

22

CAZ

I/O Integrator amplifier input

23

CINT

I/O Integrator amplifier output

24

CONTINUITY I/O Input: when LO, continuity flag on the display is off. When

HI, continuity flag is on.

Output: HI when voltage between inputs is less than +200mV

LO when voltage between inputs is more than +200mV.

25

COMMON

O Set common-mode voltage of 3.2V below V+.

26

CREF+

I/O Positive connection to external reference capacitor

27

CREF-

I/O Negative connection to external reference capacitor

28

NC

29

BUFFER

O Buffer amplifier output

30

IN_LO

I Negative input voltage terminal

31

IN_HI

I Positive input voltage terminal

32

REF_HI

I Positive reference voltage terminal

33

REF_LO

I Negative reference voltage terminal

34

DGND

O Ground reference for digital section

35

RANGE

I Pulled HIGH externally for 2V scale.

36

DP2

I When HI, decimal point 2 will be on.

37

DP1

I When HI, decimal point 1 will be on.

38

OSC2

I/O Output of first clock inverter. Input of second clock inverter.

39

INT100

I Reduce the integration time to 1/10 when RANGE is set to

high. The polarity of ADC will be ignored also.

40

OSC1

I/O Input of first clock inverter.

41

OSC3

I/O Output of second clock inverter.

42

ANNUNC

O Backplane squarewave output for driving annunctors.

43

B1, C1, CONT

O Output to LCD segment.

44

A1, G1, D1

O Output to LCD segment.