US1150

2-5

Rev. 1.2

10/28/99

The US1150 keeps a constant 1.25V between the Vsense

pin and the Vadj pin. By placing a resistor R1 across

these two pins and connecting the Vsense and Vout pin

together , a constant current flows through R1, adding

to the Iadj current and into the R2 resistor producing a

voltage equal to the (1.25/R1)*R2 + Iadj*R2 .This voltage

is then added to the 1.25V to set the output voltage.

This is summarized in the above equation. Since the

minimum load current requirement of the US1150 is 10

mA , R1 is typically selected to be a 121

Ω resistor so

that it automatically satisfies this condition. Notice that

since the Iadj is typically in the range of 50uA it only

adds a small error to the output voltage and should be

considered when very precise output voltage setting is

required.

Load Regulation

Since the US1150 has separate pins for the output (Vout)

and the sense (Vsense), it is ideal for providing true re-

mote sensing of the output voltage at the load.This

means that the voltage drops due to parasitic resistance

such as PCB traces between the regulator and the load

are compensated for using remote sensing. Figure 3

shows a typical application of the US1150 with remote

sensing.

Figure 3 - Schematic showing connection for best

load regulation

Stability

The US1150 requires the use of an output capacitor as

part of the frequency compensation in order to make the

regulator stable. Typical designs for the microproces-

sor applications use standard electrolytic capacitors with

typical ESR in the range of 50 to 100 m

Ω and an output

capacitance of 500 to 1000uF. Fortunately as the ca-

pacitance increases, the ESR decreases resulting in a

fixed RC time constant. The US1150 takes advantage of

this phenomena in making the overall regulator loop

stable.

For most applications a minimum of 100uF aluminum

electrolytic capacitor such as Sanyo, MVGX series

,Panasonic FA series as well as the Nichicon PL series

insures both stability and good transient response.

Thermal Design

The US1150 incorporates an internal thermal shutdown

that protects the device when the junction temperature

exceeds the allowable maximum junction temperature.

Although this device can operate with junction tempera-

tures in the range of 150

°C ,it is recommended that the

selected heat sink be chosen such that during maxi-

mum continuos load operation the junction temperature

is kept below this number. The example below shows

the steps in selecting the proper surface mount pack-

age.

Assuming, the following conditions:

Vout=2.7V

Vin=3.3V

Vctrl=5V

Iout=2A DC Avg

Calculate the maximum power dissipation using the fol-

lowing equation:

Pd=Iout*(Vin-Vout) + (Iout/60)*(Vctrl - Vout)

Pd=2*(3.3-2.7) + (2/60)*(5-2.7)=1.28 W

Using table below select the proper package and the

amount of copper board needed.

Pkg

Copper

Max Pd

Max Pd

Area

TO263 1.4"X1.4"

25

4.4W

3.6W

TO263 1.0"X1.0"

30

3.7W

3.0W

TO263 0.7"X0.7"

35

3.1W

2.6W

TO263 Pad Size

45

2.4W

2.0W

SO8

1.0"X1.0"

55

2.0W

1.63W

Note: Above table is based on the maximum junction

temperature of 135

°C.

As shown in the above table, any of the two packages

will do the job. For low cost applications the SO8 pack-

age is recommended.

1150app3-1.0

R1

R2

Vin

Vctrl

RL

US1150

Vsense

Adj

Vout

Vctrl

Vin