AD6659

Rev.

| Page 7 of

40

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS disabled, unless otherwise noted.

Table 4.

Parameter

Temp

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

480

MHz

Conversion Rate1

Full

3

80

MSPS

Full

12.5

ns

Full

6.25

ns

Full

1.0

ns

Full

0.1

ps rms

DATA OUTPUT PARAMETERS

Full

3

ns

Full

3

ns

Full

0.1

ns

Pipeline Delay (Latency)

Full

9

Cycles

With NSR Enabled

Full

10

Cycles

With QEC Enabled

Full

11

Cycles

Wake-Up Time2

Full

350

μs

Standby

Full

260

ns

OUT-OF-RANGE RECOVERY TIME

Full

2

Cycles

N – 9

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N

N – 8N – 7N – 6N – 5

VIN

CLK+

CLK–

CH A/CH B DATA

DCOA/DCOB

Figure 2. CMOS Output Data Timing