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LTC3604

3604f

Each time a power MOSFET gate is switched from low

to high to low again, a packet of charge dQ moves

from VIN to ground. The resulting dQ/dt is a current

out of INTVCC that is typically much larger than the DC

control bias current. In continuous mode, IGATECHG

= f(QT + QB), where QT and QB are the gate charges

of the internal top and bottom power MOSFETs and f

is the switching frequency. For estimation purposes,

(QT + QB) on the LTC3604 is approximately 1nC.

To calculate the total power loss from the LDO load,

simply add the gate charge current and quiescent cur-

rent and multiply by VIN:

PLDO = (IGATECHG + IQ) • VIN

3. Other “hidden” losses such as transition loss, cop-

per trace resistances, and internal load currents can

account for additional efﬁciency degradations in the

overall power system. Transition loss arises from the

brief amount of time the top power MOSFET spends in

the saturated region during switch node transitions. The

LTC3604 internal power devices switch quickly enough

that these losses are not signiﬁcant compared to other

sources.

Other losses, including diode conduction losses during

dead time and inductor core losses, generally account

for less than 2% total additional loss.

Thermal Considerations

The LTC3604 requires the exposed package backplane

metal (PGND pin on the QFN, SGND pin on the MSOP

package) to be well soldered to the PC board to provide

good thermal contact. This gives the QFN and MSOP

packages exceptional thermal properties, compared to

other packages of similar size, making it difﬁcult in normal

operation to exceed the maximum junction temperature

of the part. In many applications, the LTC3604 does not

dissipate much heat due to its high efﬁciency and low

thermal resistance package backplane. However, in applica-

tions in which the LTC3604 is running at a high ambient

temperature, high input voltage, high switching frequency,

and maximum output current, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

APPLICATIONS INFORMATION

both power switches will be turned off until temperature

decreases approximately 10°C.

Thermal analysis should always be performed by the user

to ensure the LTC3604 does not exceed the maximum

junction temperature.

The temperature rise is given by:

TRISE = PDθJA

where PD is the power dissipated by the regulator and θJA

is the thermal resistance from the junction of the die to

the ambient temperature.

Consider the example in which an LTC3604EUD is operat-

ing with IOUT = 2.5A, VIN = 12V, f = 1MHz, VOUT = 1.8V,

and an ambient temperature of 25°C. From the Typical

Performance Characteristics section the RDS(ON) of the top

switch is found to be nominally 130mΩ while that of the

bottom switch is nominally 100mΩ yielding an equivalent

power MOSFET resistance RSW of:

RDS(ON)TOP • 1.8/12 + RDS(ON)BOT • 10.2/12 = 105mΩ.

From the previous section, IGATECHG is ~1mA when f =

1MHz, and the spec table lists the maximum IQ to be 1mA.

Therefore, the total power dissipation due to resistive

losses and LDO losses is:

PD = IOUT2 • RSW + VIN • (IGATECHG + IQ)

PD = (2.5A)2 • (0.105Ω) + 12V • 2mA = 680mW

The QFN 3mm

×3mmpackagejunction-to-ambientthermal

resistance,

θJA, is around 45°C/W. Therefore, the junction

temperature of the regulator operating in a 25°C ambient

temperature is approximately:

TJ = 0.680W • 45°C/W + 25°C = 56°C

Remembering that the above junction temperature is

obtained from an RDS(ON) at 25°C, we might recalculate the

junction temperature based on a higher RDS(ON) since it

increaseswithtemperature.Redoingthecalculationassum-

ing that RSW increased 15% at 56°C yields a new junction

temperature of 66°C. If the application calls for a signiﬁ-

cantly higher ambient temperature and/or higher switching

frequency, care should be taken to reduce the temperature

rise of the part by using a heat sink or air ﬂow.

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