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LT3640 Datasheet(PDF) 4 Page - Linear Technology

Part # LT3640
Description  Dual Monolithic Buck Regulator with Power-On Reset and Watchdog Timer
PDF  24 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT3640 Datasheet(HTML) 4 Page - Linear Technology

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LT3640
4
3640p
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3640E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3640I is guaranteed and tested over the full –40°C to 125°C operating
junction temperature range.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SS1, SS2 Charge Current
SS1 = 0.5V, SS2 = 0.5V
1.4
1.9
2.5
μA
SS1 to FB1 Offset Voltage
SS1 = 0.6V
5
30
mV
SS2 to FB2 Offset Voltage
SS2 = 0.3V
5
30
mV
RST1 Threshold as Percentage of VFB
l
90
92
94
%
RST2 Threshold as Percentage of VFB
l
89
92
94
%
Undervoltage to RST Assert Time
20
μs
RST1, RST2, WDO Pull-Up Current
RST1, RST2, WDO = 0V
5
15
30
μA
RST1, RST2, WDO Output Voltage
IRST1, IRST2, IWDO = 2mA
150
250
mV
RST1, RST2 Timeout Period (tRST)
CPOR = 220pF
l
8
9.5
11
ms
Watchdog Start Delay Time (tDLY)
CWDT = 820pF
14
16
18
ms
Watchdog Upper Boundary (tWDU)
CWDT = 820pF
l
27
32
35
ms
Watchdog Lower Boundary (tWDL)
CWDT = 820pF
l
1.68
2
2.2
ms
WDI Pull-Up Current
WDI = 1.2V
2
μA
WDI Voltage Threshold
0.55
0.85
1.15
V
WDI Low Minimum Pulse Width
300
ns
WDI High Minimum Pulse Width
300
ns
WDE Pull-Down Current
WDE = 2V
1
μA
WDE Threshold
l
0.5
0.7
0.9
V
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VIN2 = 3.3V, EN/UVLO = 12V, EN2 = 3.3V, unless otherwise noted.
Note 3: SW1, SW2 current limit is guaranteed by design and/or correlation
to static test. Slope compensation reduces current limit at higher duty
cycle.
Note 4: The oscillator cycle is extended when DA current exceeds its limit.
DA current limit is flat over duty cycle.
Note 5: If the SW2 NMOS current exceeds its limit at the start of an
oscillator cycle, the PMOS will not be turned on in the cycle.
Note 6: The QFN switch RDS(ON) is guaranteed by correlation to wafer level
measurement.
Note 7: Absolute maximum voltage at VIN and RUN/SS pin is 55V for
nonrepetitive one second transients, and 36V for continuous operation.
ELECTRICAL CHARACTERISTICS



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