PixArt Imaging Inc.

PAS202BCB/PAS202BBB

CMOS Image Sensor IC

All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.

9

PixArt Imaging Inc.

V2.0, May 2002

registers value inside PAS202BCB/PAS202BBB can be programming via this way. (Please refer to Fig 4.3.)

4.2.2 Slave transmits data to master (read cycle)

During read cycle, the master generates start condition and then place the 1

slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was

also placed on SDA line by PAS202BCB/PAS202BBB. The 8 bit data was read from PAS202BCB/PAS202BBB

internal control register that address was assigned by previous write cycle. Follow the master acknowledgment,

the PAS202BCB/PAS202BBB place the next 8 bits data (address is increment automatically) on SDA line and

then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read,

Am is no longer generated by master but instead by keep SDA line high. The slave (PAS202BCB/PAS202BBB)

must releases SDA line to master to generate STOP condition. (Please refer to Fig 4.3.)

Fig 4.3 Data Transfer Format

S

SLAVE ADDRESS

(7 BITS)

RW

A

DATA (8 BIT)

Am

DATA

1

P

1ST BYTE

2ND BYTE

n BYTE

NO ACK IN LAST

BYTE

Am

DATA

SDA

SCL

S

Start

Condition

1-7

8

9

1-7

8

9

1-7

8

9

P

Stop

Condition

ACK

from

Receiver

Data

ACK

from

Receiver

Data

ACK

from

Receiver

R/W

Address