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HY5PS12421AF Datasheet(PDF) 22 Page - Hynix Semiconductor |
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HY5PS12421AF Datasheet(HTML) 22 Page - Hynix Semiconductor |
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22 / 37 page  Rev. 0.2 / Mar. 2005 22 512Mb A-ver. DDR2 SDRAM Parameter Symbol DDR2-800 DDR2-667 Unit Note min max min max DQ output access time from CK/CK tAC -400 +400 -450 +450 ps DQS output access time from CK/CK tDQSCK -350 +350 -400 +400 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min(tCL, tCH) - min(tCL, tCH) - ps 11,12 Clock cycle time, CL=x tCK 2500 3000 8000 ps 15 DQ and DM input setup time tDS(base) 50 - 100 - ps 6,7,8,20 DQ and DM input hold time tDH(base) 125 - 175 - ps 6,7,8,21 Control & Address input pulse width for each input tIPW 0.6 -0.6 - tCK DQ and DM input pulse width for each input tDIPW 0.35 -0.35- tCK Data-out high-impedance time from CK/CK tHZ - tAC max - tAC max ps 18 DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps 18 DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps 18 DQS-DQ skew for DQS and associated DQ signals tDQSQ -200 -240 ps 13 DQ hold skew factor tQHS -300 -340 ps 12 DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps First DQS latching transition to associated clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 10 Write preamble tWPRE 0.35 - 0.35 - tCK Address and control input setup time tIS(base) 175 - 200 - ps 5,7,9,22 Address and control input hold time tIH(base) 250 - 275 - ps 5,7,9,23 Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 19 Read postamble tRPST 0.4 0.6 0.4 0.6 tCK 19 Activate to precharge command tRAS 45 70000 45 70000 ns 3 Active to active command period for 1KB page size products tRRD 7.5 - 7.5 - ns 4 Active to active command period for 2KB page size products tRRD 10 - 10 - ns 4 Four Active Window for 1KB page size products tFAW 37.5 - 37.5 - ns Four Active Window for 2KB page size products tFAW 50 - 50 - ns CAS to CAS command delay tCCD 2 2 tCK Write recovery time tWR 15 - 15 - ns Auto precharge write recovery + precharge time tDAL WR+tRP - WR+tRP - tCK 14 Internal write to read command delay tWTR 7.5 -7.5 - ns Internal read to precharge command delay tRTP 7.5 7.5 ns 3 Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns Exit self refresh to a read command tXSRD 200 - 200 - tCK Exit precharge power down to any non-read command tXP 2 - 2 - tCK Exit active power down to read command tXARD 2 2 tCK 1 Exit active power down to read command (Slow exit, Lower power) tXARDS 8 - AL 7 - AL tCK 1, 2 |
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