HT68F20 datasheet(114/232 Pages) HOLTEK

114 / 232 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

HT68FU30/HT68FU40/HT68FU50/HT68FU60

Rev.1.10

114

February 1, 2010

As the name of the mode suggests, after a comparison

is made, the TM output pin, will change state. The TM

output pin condition however only changes state when

an TnAF or TnBF interrupt request flag is generated af-

ter a compare match occurs from Comparator A or Com-

parator B. The TnPF interrupt request flag, generated

from a compare match from Comparator P, will have no

effect on the TM output pin. The way in which the TM

output pin changes state is determined by the condition

of the TnAIO1 and TnAIO0 bits in the TMnC1 register for

ETM CCRA, and the TnBIO1 and TnBIO0 bits in the

TMnC2 register for ETM CCRB. The TM output pin can

be selected using the TnAIO1, TnAIO0 bits (for the

TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0,

TPnB_1 or TPnB_2 pins) to go high, to go low or to tog-

gle from its present condition when a compare match

occurs from Comparator A or a compare match occurs

from Comparator B. The initial condition of the TM out-

put pin, which is setup after the TnON bit changes from

low to high, is setup using the TnAOC or TnBOC bit for

TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note

that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are

zero then no pin change will take place.

ETM CCRA Compare Match Output Mode

- TnCCLR = 0

Note:

1. With TnCCLR = 0 the Comparator P match will clear the counter

2. TPnA output pin controlled only by TnAF flag

3. Output pin reset to initial state by TnON bit rising edge

HT68F20 Datasheet(PDF) 114 Page - Holtek Semiconductor Inc