None of the inputs to U1 or U2 of the DRF1300 are isolated for direct connection to a ground referenced power supply or control circuitry.

Isolation appropriate to the application is the responsibility of the end user. It is imperative that high output currents be restricted to

the Source (14, 16, 18) and drain (15, 17) pins by design. See DRF100 for more information on Driver IC used in the device.

The Function (FN, pin 3 or pin 9) is the invert or non-invert select Pin, it is Internally held high.

Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583

4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743 and foreign patents. us and Foreign patents pending. All Rights Reserved.

DRF1301

The test circuit illustrated in Figure 2 was used to evaluate the DRF1301 (available as an evaluation board DRF13XX/EVALSW.) The input

control signal is applied via IN and SG pins using RG188. This provides excellent noise immunity and control of the signal ground currents.

The +V

for this function must be capable of supporting the RMS currents and frequency of the gate load. A 50 Ohm (RL) load is used to evaluate the

output performance.

Figure 2, DRF1301 Test Circuit

Truth Table * Referenced to SG

FN (pin 3)

IN (pin 4)

MOSFET U1

HIGH

HIGH

ON

HIGH

LOW

OFF

LOW

HIGH

OFF

LOW

LOW

ON

Truth Table * Referenced to SG

FN (pin 9)

IN (pin 10)

MOSFET U2

HIGH

HIGH

ON

HIGH

LOW

OFF

LOW

HIGH

OFF

LOW

LOW

ON