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Copyright © 2009

Microsemi

Rev. 1.3 2009-02-23

Analog Mixed Signal Group

2381 Morse Avenue, Irvine, CA 92614, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308

7

PD Operating Status

LED1

LED2

IEEE802.3af – ON

ON

OFF

IEEE802.3at – ON

ON

ON

IEEE802.3af -

OVL/SC

Blink at 1Hz

OFF

IEEE802.3at -

OVL/SC

Blink at 1Hz

Blink at 1Hz

Vmain out of range

Blink at 4Hz

OFF

Layout Design Guidelines

(See Figure 3 for layout example)

Isolation & Termination – as specified in the IEEE

standard, certain isolation requirements need to be

met in all PoE equipment. In addition, EMI limitations

should be considered, according to FCC and

European EN regulations.

These requirements are taken into account by PoE

switch vendors, while designing the switch circuitry.

However, when a PoE device is integrated into a

switch, special design considerations must be taken

into account, due to the unique combination of Data

and Power circuitries.

The next paragraphs define these requirements and

provide recommendations for their implementation,

so as to assist designers in meeting those

requirements and in integrating PoE Chipset.

Isolation - As specified in the IEEE standard,

1500Vac rms isolation is required between the main

board circuitry of the switch, including protective and

frame ground and the PoE circuitry.

Isolating the Stacked Modular Jack Assembly

The IEEE standard requires 1500 Vrms isolation

between PoE voltages and frame ground (EGND).

Note that RJ-45 jack assemblies may have a metal

cover that reach almost to the PCB surface.

Proper traces clearance (at least 80 mils) are to be

maintained between EGND traces for the RJ-45

modular jack assembly metal covering and adjacent

circuit paths and components.

To prevent 1500 Vrms isolation violation, it is

necessary to provide layout clearances of PoE

traces, on the top layer, in the vicinity of the RJ-45

connector assemblies.

PoE Output Ports’ Filtering and Terminations: A

switch normally creates a noisy environment. In

order to meet the EMI requirements, good filtering

and line terminations may be needed when

connecting the PoE circuit outputs to the switch

circuitry (see Figure 1). Note that in most PoE

systems, it is recommended to use 0 Ohms resistors

for R100 and R101. However, certain systems may

benefit from the 75Ohm value. It is recommended

that filtering provisions are utilized.

A circuitry for the recommended filter includes:

•

A common mode choke for conducted EMI

performances

•

Output differential capacitor filter for

radiated EMI performances

•

Y-capacitive/resistive network to chassis

Since each system is a unique EMI case, this circuit

is a good starting point for EMI suppression.

Out (+)

Out(-)

Port_ Pos

Port_ N eg

R100

R 10 1

C 100

C101

L100

C102

C103

Figure 1: Recommended EMI Filter

noise accumulated on the lines between the filter

and the port connectors, it is recommended to

assemble this circuitry as close as possible to the

port connectors.

PoE circuitry Trace Clearance - PoE technology

involves voltages as high as 57VDC. Thus, plan

adjacent traces for 100V operational creepage.

Operational creepage should be maintained to

prevent breakdown between traces carrying these

potentials.

Locating PoE Circuitry in a Switch - Placement of the

PoE circuitry must be as close as possible to the