WM5615CD datasheet(8/12 Pages) WOLFSON

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Wolfson Microelectronics

WM5615

Serial Interface

The WM5615 uses a three-wire serial interface which is

compatible with SPI, QSPI (CPOL = CPHA = 0) and

Microwire standards as shown in figures 2 and 3. The

DAC is programmed by writing two 8-bit words, MSB

first (see Block Diagram and Timing Diagram). 16 bits of

serial data are clocked into the DAC in the following or-

der, 4 fill (dummy) bits, 10 data bits and 2 sub-LSB Xs.

The 4 dummy bits are not normally needed and are re-

quired only when DACs are daisy chained. The 2 sub-

LSB Xs, however, are always needed because the input

while SCLK is low. Data is clocked in on the SCLK rising

edge while CS is low. The serial input data is held in a 16-

bit serial shift register. On the CS rising edge, the ten

data-bits are transferred to the DAC register and update

the DAC. With CS high, data cannot be clocked into the

DIN terminal.

The WM5615 receives data in 16-bit blocks. The SPI and

Microwire interfaces output data in 8-bit blocks requiring

two write cycles to input data to the DAC. The QSPI

interface allows variable data output from 8 to 16 bits so

can load into the DAC in one write cycle.

Buffer Amplifier

The output buffer is a rail-to-rail output CMOS op amp.

Max. setting time is 12.5µs to +/-0.5 LSB of final value.

The output is short-circuit protected and can drive a 2k

Ω

load with a 100pF load capacitance.

External Reference

The external voltage input is buffered and must be posi-

tive but less than VDD - 2V. The reference voltage deter-

mines the DAC full-scale output. Since the reference

terminal is buffered, the DAC input resistance is not code

dependent and is 10M

Ω minimum. The REFIN input ca-

pacitance is typically 5pF.

Digital Interface

The digital inputs are designed to be compatible with TTL

or CMOS logic levels. However, to achieve the lowest

power dissipation, the digital inputs should be driven with

rail-to-rail CMOS logic. With TTL logic levels, the power

requirement increases by a factor of approximately two.

INPUT*

OUTPUT

1111

11 (xx)

+2(V

REFIN

)

1000

0000

01 (xx)

+2(V

REFIN

)

1000

0000

00 (xx)

+2(V

REFIN

)

= V

REFIN

0111

1111

11 (xx)

+2(V

REFIN

)

0000

01 (xx)

+2(V

REFIN

)

0000

00 (xx)

Detailed Description (Continued)

1023

1024

513

1024

511

1024

Table 1 - Binary Code Table

(0V to 2VREFIN Output), Gain = 2

512

1024

* A 10-bit data word with two sub-LSB Xs must be

written since the DAC input latch is 12-bits wide.

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