WM5615

Wolfson Microelectronics

5

Setup time, DIN before SCLK high

45

ns

Hold time, DIN valid after SCLK high

0

ns

Setup time, CS low to SCLK high

1

ns

Setup time CS high to SCLK high

50

ns

Hold time, SCLK low to CS low

1

ns

Hold time, SCLK low to CS high

0

ns

Pulse duration, min. chip select pulse width height

20

ns

Pulse duration, SCLK low

18

ns

Pulse duration, SCLK high

tw (CH)

18

ns

Output Switching Specification

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Output slew rate

SR

Ω

0.3

0.5

V/

µs

Output settling time

12.5

µs

Ω (see note 9)

Glitch energy

DIN = All 0s to all 1s

5

nV

Signal to noise + distortion

S/(N+D)

60

dB

2.048 V DC, code 512

Note 9:

Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital

input code change from code zero to 1023 rising and 1023 to 64 falling.

Digital Input Timing Specifications

Analogue Output Dynamic Performance

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time

50

ns

Reference feedthrough

Input code = 00

-80

dB

(see note 10)

Reference input bandwidth

Input code = 512

100

kHz

(see note 10)

Note 10: Reference feedthrough and bandwidth are measured at the DAC output with Vref input = 2Vpp at 1kHz +

2.048V DC

reference input (REFIN)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT