WM8170 datasheet(22/41 Pages) WOLFSON

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WM8170

Product Preview Rev 1.0

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 March 2000

EXTENDED DC CORRECTION MODE

The WM8170 device has extended Black Level Correction Circuitry, which make it suitable for

continuous video applications. The Black Level Clamp correction circuitry in the WM8170 consists of

two main components, an Analogue correction loop which is used to remove the majority of the dc

offset using analogue circuit techniques, and a digital filter which can be programmed with different

filter responses. Figure 17 shows the Black Level Correction Circuitry in Detail.

BIPOLAR

OUTPUT

8-Bit DAC

UP/DOWN

COUNTER

COMPARATOR

10-BIT

ADC

PGA

Output from

Sample and Hold

CONTROL

BLCENB

ANDUR[6:0]

DIGDUR[3:0]

DIGITAL ENABLE

TO OUTPUT

PINS D[9:0]

ADDER

DIVIDE

Average error

between ADC

O/P code and

TARGET code

during optically

black pixels

ANALOGUE ENABLE

TARGET[7:0]

STOPDC

VRB

VRT

DIGITAL GAIN CONTROL

IIR

FILTER

PRELOAD

DATA

PRELOAD

ENABLE

IIR ENABLE

8-BIT

DAC

SEL

MUX

INTERNAL

ANALOGUE

ENABLE

ENINTBLC

Figure 17 Black Level Correction Circuitry

In order to control the Correction Circuitry there are two Pulse Generators incorporated within the

WM8170. These Pulse Generators and their associated Control Register Bits are shown in Figure 18.

This diagram shows all signals associated with the Pulse Generators. External signals are shown

with a O, internal register settings with a *. One Pulse Generator is used to generate an internal pulse

relative to the falling edge of the BLCENB input. This pulse, called INTBLCENB, is then steered

using the Steering Circuitry to be either the enable for the Analogue Correction Circuitry or for the

Digital IIR filter. This allows the user to select which lines of the input video frame the Analogue

correction loop will be enabled, and for which lines the IIR Filter will be enabled.

INTBLCENB

PULSE

GENERATOR

AREA

PULSE

GENERATOR

INTERNAL

CLOCK

GENERATION

CLK

INTBLCENB

STEERING

CIRCUITRY

INTBLCENB

ACON*[1:0]=10

ACON*[1:0]=11

INTERNAL ANALOGUE

LOOP ENABLE

INTERNAL IIR FILTER

ENABLE

ENVD*

ENHD*

BLCENB

SHP

SHD

Figure 18 WM8170 Pulse Generators

Following a falling edge on the Analogue Correction Loop Enable the internal circuitry is active for

ANDUR*4 pixels, which allows the majority of the DC error to be removed by the analogue circuitry.

After this has completed the remaining offset is removed by a digital clamp that averages the ADC

error from the programmed TARGET value for 2

DIGDUR pixels and subsequently subtracts that

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