Production Data

WM8720

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 November 2000

7

DEVICE DESCRIPTION

WM8720 is a complete stereo audio digital-to-analogue converter, including digital interpolation filter,

multibit sigma delta with dither, switched capacitor multibit stereo DAC and output smoothing filters.

Control of internal functionality of the device is by either hardware control (pin programmed) or

software control (serial interface). The MODE pin selects between hardware and software control. In

software control mode, an SPI type interface is used. This interface may be asynchronous to the

audio data interface. Control data will be re-synchronized to the audio processing internally.

The device is pin compatible with the PCM1720, but uses additional pins that are not used on that

device to achieve greater user flexibility.

Operation using system clock of 256fs or 384fs is provided. Selection between clock rates is being

automatically controlled in hardware mode, or serial controlled when in software mode. Sample rates

(fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input.

The data interface supports normal (Japanese right justified) and I

delayed) interface formats, in both ‘packed’ and unpacked forms. When in hardware mode, the three

serial interface pins become control pins to allow selection of input data format type (I

input word length (16, 18, 20, or 24-bit) and de-emphasis function.

SYSTEM CLOCK

The system clock for WM8720 must be either 256fs or 384fs, where fs is the audio sampling

frequency (LRCIN) typically 32kHz, 44.1kHz, 48 or 96kHz. The system clock is used to operate the

digital filters and the noise shaping circuits.

WM8720 has a system clock detection circuitry that automatically determines what the system clock

frequency relative to the sampling rate is (to within

±8 system clocks). If greater than 8 clocks error,

then the interface shuts down the DAC and mutes the output. The system clock should be

synchronised with LRCIN, but WM8720 is tolerant of phase differences or jitter on this clock. Severe

distortion in the phase difference between LRCIN and the system clock will be detected, and cause

the device to automatically resynchronise. If the externally applied LRCIN slips in phase by more

than half the internal LRCIN period, which is derived from master clock, then the interface

resynchronises. Such a case would, for example, occur if repeated LRCIN clocks were received with

only 252 systems clocks per period. In this case the interface would resynchronise every 64 LRCIN

periods. During resynchronisation, the device will either repeat the previous sample, or drop the next

sample, depending on the nature of the phase slip. This will ensure no discernible “click “ at the

analogue outputs during resynchronisation. Table 1 shows the typical system clock frequency inputs

for the WM8720.

SYSTEM CLOCK FREQUENCY (MHZ)

SAMPLING RATE (LRCIN)

256fs

384fs

32kHz

8.192

12.288

44.1kHz

11.2896

16.9340

48kHz

12.288

18.432

96kHz

24.576

36.864

Table 1 System Clock Frequencies Versus Sampling Rate

AUDIO DATA INTERFACE

The Serial Data interface to WM8720 is fully compatible with both normal (MSB first, right-justified) or

I

the number of data bits, i.e. normally 32 in 16-bit mode) or unpacked (more than 32 bit clocks per

LRCIN period).

The WM8720 will automatically detect 16-bit packed data being sent to the device in normal mode,

and accept the data in this input format accordingly.

I

DESCRIPTION

0

Normal format (MSB-first, right justified)

1I

Table 2 Serial Interface Formats