WM8740

Advanced Information

WOLFSON MICROELECTRONICS LTD

AI Rev 1.7 July 2000

14

DIFFERENTIAL MONO MODE

Using bits 4 and 5, the differential output mode may be selected to be one of normal stereo, reversed

stereo, mono left or mono right, as shown in Table 19.

DIFF[1:0]

B[4:5])

DIFFERENTIAL OUTPUT MODE

00

Stereo

01

Stereo reverse.

10

Mono left – differential outputs.

VOUTL is left channel.

VOUTR is the negative of left channel.

11

Mono right – differential outputs.

VOUTL is the negative right channel.

VOUTR is right channel.

Table 19 Differential Output Modes

Using these controls a pair of WM8740 devices may be used to build a dual differential stereo

implementation with higher performance and differential output.

Note: DIFFHW mode pin may be used to achieve the same result by hardware means.

CLOCK LOSS DETECTOR DISABLE

CDD (REG4, B6)

L

Clock loss detector on

R

Clock loss detector off

Table 20 Clock Loss Detector Disable

When the system clock is inactive for approximately 100

µs, the clock loss detector circuit detects the

loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.

Setting the CDD bit disables this behaviour.

MUTE MODES

The device has various mute modes.

ANALOGUE

DIGITAL FILTER

ANRES

ANMUTE

Reg bit OPE = ‘1’

Unaffected

Asserted

MUTEB pin

Gain ramped to zero

On release volume ramps

to previous value

Asserted when

gain = 0

AUTOMUTE

(detect 1024 zero

input samples)

Automute has no effect on digital

filters

Asserted after

1024 zero input

samples if IZD = 1

Reg bit MUT

As MUTEB pin

As MUTEB pin

Gain = 00

(left & right)

Gain = -

∞dB

Asserted

RAM initialise

Gain initialised to 0dB

Asserted

Loss of system

clock

Not running (no clock). On clock

restart, filters initialised, RAM

initialised. Registers unchanged

Asserted

Asserted

No LRCLK or invalid

SCLK/LRCLK ratio

Filters initialised, RAM initialised.

Registers unchanged

Asserted

Asserted

RB

Reset – gain initialised to 0dB

Asserted

Asserted

Power-on reset

Reset

Asserted

Asserted

Table 21 Mute Modes