WM9701A

Production Data

WOLFSON MICROELECTRONICS LTD.

PD Rev 3.2 January 2001

10

SLOT #

SYNC

OUTGOING

STREAMS

INCOMING

STREAMS

TAG PHASE

TAG

CMD

ADR

CMD

DATA

PCM

LEFT

PCM

RIGHT

OPT

MDM CDC

RSRVD

RSRVD

RSRVD

RSRVD

RSRVD

RSRVD

RSRVD

TAG

CMD

ADR

CMD

DATA

PCM

LEFT

PCM

RIGHT

OPT

MDM CDC

RSRVD

RSRVD

RSRVD

RSRVD

RSRVD

RSRVD

RSRVD

DATA PHASE

01

234

56

789

10

11

12

Figure 7 AC’97 Standard Bi-directional Audio Frame

SYNC

BIT_CLK

SDATA_OUT

VALID

FRAME

SLOT(1)

OUT

SLOT(2)

SLOT(12)

’0’

’0’

’0’

19

0

19

0

19

0

19

0

TAG PHASE

DATA PHASE

20.8

µS (48kHz)

12.288MHz

81.4nS

END OF PREVIOUS

AUDIO FRAME

TIME SLOT ’VALID’ BITS

(’1’ = TIME SLOT CONTAINS

VALID PCM DATA)

SLOT (1)

SLOT (2)

SLOT (3)

SLOT (12)

Figure 8 AC-link Audio Output Frame

The data streams currently defined by the AC’97 specification include:

PCM playback - 2 output slots

2 channel composite PCM output stream

PCM record data - 2 input slots

2 channel composite PCM input stream

Control 2 output slots

Control register write port

Status 2 input slots

Control register read port

Optional modem line Codec output - 1

output slot

Modem line Codec DAC input stream

(Not supported by WM9701A)

Optional modem line Codec input - 1

input slot

Modem line Codec ADC output stream

(Not supported by WM9701A)

Optional dedicated microphone input -

1 input slot

Dedicated microphone input stream in support of

stereo AEC, and/or other voice applications.

(Not supported by WM9701A)

Synchronisation of all AC-link data transactions is signalled by the WM9701A controller. WM9701A

drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with a

synchronisation signal to construct audio frames.

SYNC fixed at 48 kHz, is derived by dividing down the serial clock (BIT_CLK). BIT_CLK, fixed at

12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming

time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-

link data, (WM9701A for outgoing data and the AC’97 controller for incoming data), samples each

serial bit on the falling edges of BIT_CLK.

The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid

tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0

indicates that the corresponding time slot within the current audio frame has been assigned to a data

stream, and contains valid data. If a slot is “tagged” invalid, it is the responsibility of the source of the

data, (WM9701A for the input stream, AC’97 controller for the output stream); to stuff all bit positions

with 0s during that slot’s active time.