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SS8018

POR AND UVLO

The SS8018 has a volatile memory. To prevent ambigu-

ous power-supply conditions from corrupting the data in

memory and causing erratic behavior, a POR voltage de-

tector monitors VCC and clears the memory if VCC falls

below 1.7V (typical, see Electrical Characteristics table).

When power is first applied and VCC rises above 1.7V

(typical), the logic blocks begin operating, although reads

A second VCC comparator, the ADC UVLO comparator,

prevents the ADC from converting until there is sufficient

headroom (VCC= 2.8V typical).

ALERT

Fault Queue

until consecutive out of limit measurements have

reached the queue number. The mapping of fault queue

register (ALERTFQ, 22h) value to fault queue number is

shown in the Table 9.

Table 9. Alert Fault Queue

ALERTFQ

VALUE

FAULT QUEUE NUMBER

XXXX000X

1

XXXX001X

2

XXXX010X

3

XXXX011X

3

XXXX100X

4

XXXX101X

4

XXXX110X

4

XXXX111X

4

Operation of The THERM Function

the SS8018 to set the temperature limit above which the

THERM

pin asserts low and the bit 1, of status byte will

be set to 1 corresponding to remote and local over tem-

perature. These two bits won’t be cleared to 0 by read-

ing status byte it the over temperature condition remain.

A hysteresis value is provided by writing the register 21h

to set the temperature threshold to release the

THERM

pin alarm state, The releasing temperature is

the value of register 19h, 20h minus the value in register

21h. The format of register 21h is 2’s complement. The

THERM

signal is open drain and requires a pull-up re-

sistor to power supply.

Rev.2.01 6/06/2003