DS1706 datasheet(3/12 Pages) MAXIM

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DS1705/DS1706

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Watchdog Timer

The watchdog timer function forces WDS signals active when the ST input is not clocked within the 1

second time-out period. Time-out of the watchdog starts when RST (or RST) becomes inactive. If a high-

to-low transition occurs on the ST input pin prior to time-out, the watchdog timer is reset and begins to

time out again. If the watchdog timer is allowed to time out, the WDS signal is driven active (low) for a

minimum of 130 ms. The ST input can be derived from many microprocessor outputs. The typical signals

used are the microprocessors address signals, data signals, or control signals. When the microprocessor

functions normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to

time-out. To guarantee that the watchdog timer does not time out, a high-to-low transition must occur at

or less than the minimum watchdog time-out of 1 second. A typical circuit example is shown in Figure 6.

MICROMONITOR BLOCK DIAGRAM

Figure 1

40k



180k



PUSH-BUTTON RESET

Figure 2

DS1706 Datasheet(PDF) 3 Page - Maxim Integrated Products