74ABT657_3

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Product data sheet

Rev. 03 — 15 March 2010

8 of 17

NXP Semiconductors

74ABT657

Octal transceiver with parity generator/checker; 3-state

10. Dynamic characteristics

[1]

These delay times reflect the 3-state recovery time only and do not include the delay through the buffers and the parity check circuitry

which affect the ERROR output. To ensure valid information at the ERROR pin, time must be allowed for the signal to propagate

through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output. Valid data at the

ERROR pin

≥ (B to A) + (A to PARITY).

Table 7.

Dynamic characteristics

GND = 0 V; for test circuit, see Figure 9.

Symbol Parameter

Conditions

25

°C; V

−40 °C to +85 °C;

Unit

Min

Typ

Max

Min

Max

LOW to HIGH

propagation delay

An to Bn or Bn to An; see Figure 6

1.1

2.5

4.1

1.1

4.6

ns

An to PARITY; see Figure 5 and 6

2.5

5.1

6.7

2.5

8.1

ns

ODD/EVEN to PARITY and ERROR;

see Figure 5 and 6

1.7

3.5

4.6

1.7

5.3

ns

Bn to ERROR; see Figure 5 and 6

3.9

7.3

10.2

3.9

12.3

ns

PARITY to ERROR; see Figure 5 and 6

2.7

4.5

5.9

2.7

7.7

ns

HIGH to LOW

propagation delay

An to Bn or Bn to An; see Figure 6

1.2

3.0

3.9

1.2

4.3

ns

An to PARITY; see Figure 5 and 6

2.8

5.0

7.4

2.8

8.9

ns

ODD/EVEN to PARITY and ERROR;

see Figure 5 and 6

1.9

3.7

5.1

1.9

5.8

ns

Bn to ERROR; see Figure 5 and 6

4.0

7.9

10.5

4.0

12.9

ns

PARITY to ERROR; see Figure 5 and 6

3.2

5.2

6.7

3.2

8.1

ns

OFF-state to HIGH

propagation delay

see Figure 7 and 8

[1]

1.3

3.6

5.5

1.3

6.5

ns

OFF-state to LOW

propagation delay

see Figure 7 and 8

[1]

1.9

4.2

5.3

1.9

6.5

ns

HIGH to OFF-state

propagation delay

see Figure 7 and 8

2.4

3.6

5.6

2.4

6.2

ns

LOW to OFF-state

propagation delay

see Figure 7 and 8

2.2

3.4

7.3

2.2

7.8

ns