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74F269 Datasheet(PDF) 12 Page - NXP Semiconductors |
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74F269 Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 19 page ![]() 74F269_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 05 — 25 March 2010 12 of 19 NXP Semiconductors 74F269 8-bit bidirectional binary counter The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VM =1.5 V VOL and VOH are the typical output voltage levels that occur with the output load. Fig 11. Count enable inputs (CEP and CET) and clock input (CP) set-up and hold times 001aal302 VM tsu(L) th(L) tsu(H) th(H) VM VM VM VM VM GND VI GND VI VOH VOL CP Qn COUNT NO CHANGE CET, CEP The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VM =1.5 V VOL and VOH are the typical output voltage levels that occur with the output load. Fig 12. Up/down count control input (U/D) and clock input (CP) set-up and hold times 001aal303 VM tsu(L) th tsu(H) th VM VM VM VM VM U/D CP VI GND VI VOH VOL GND Qn COUNT DOWN COUNT UP |
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