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74LVC74AD Datasheet(PDF) 6 Page - NXP Semiconductors

Part # 74LVC74AD
Description  Dual D-type flip-flop with set and reset; positive-edge trigger
PDF  16 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LVC74AD Datasheet(HTML) 6 Page - NXP Semiconductors

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74LVC74A_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 4 June 2007
6 of 16
NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
10. Dynamic characteristics
[1]
Typical values are measured at Tamb =25 °C. For VCC = 3.0 V to 3.6 V range, typical values are measured at 3.3 V.
[2]
tpd is the same as tPLH and tPHL.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter
Conditions
−40 °C to +85 °C
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation
delay
nCP to nQ, nQ; see Figure 7
[2]
VCC = 1.2 V
-
15
-
-
-
ns
VCC = 2.7 V
1.0
2.7
6.0
1.0
7.5
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
5.2
1.0
6.5
ns
nSD to nQ, nQ; see Figure 8
VCC = 1.2 V
-
15
-
-
-
ns
VCC = 2.7 V
1.0
3.2
6.4
1.0
8.0
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
5.4
1.0
7.0
ns
nRD to nQ, nQ; see Figure 8
VCC = 1.2 V
-
15
-
-
-
ns
VCC = 2.7 V
1.0
3.2
6.4
1.0
8.0
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
5.4
1.0
7.0
ns
tW
pulse width
clock HIGH or LOW; see Figure 7
VCC = 2.7 V
3.3
-
-
4.5
-
ns
VCC = 3.0 V to 3.6 V
3.3
1.3
-
4.5
-
ns
set or reset LOW; see Figure 8
VCC = 2.7 V
3.3
-
-
4.5
-
ns
VCC = 3.0 V to 3.6 V
3.3
1.7
-
4.5
-
ns
trec
recovery time
set or reset; see Figure 8
VCC = 2.7 V
1.5
-
-
1.0
-
ns
VCC = 3.0 V to 3.6 V
+1.0
−3.0
-
1.0
-
ns
tsu
set-up time
nD to nCP; see Figure 7
VCC = 2.7 V
2.2
-
-
2.2
-
ns
VCC = 3.0 V to 3.6 V
2.0
0.8
-
2.0
-
ns
th
hold time
nD to nCP; see Figure 7
VCC = 2.7 V
1.0
-
-
1.0
-
ns
VCC = 3.0 V to 3.6 V
+1.0
−0.2
-
1.0
-
ns
fmax
maximum
frequency
nCP; see Figure 7
VCC = 2.7 V
83
-
-
66
-
MHz
VCC = 3.0 V to 3.6 V
150
250
120
-
MHz
tsk(o)
output skew time VCC = 3.0 V to 3.6 V
[3]
-
-
1.0
-
1.5
ns
CPD
power
dissipation
capacitance
per flip-flop; VI = GND to VCC
[4]
VCC = 3.3 V
-
15
-
-
-
pF



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