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74LVC74AD Datasheet(PDF) 9 Page - NXP Semiconductors |
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74LVC74AD Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 16 page ![]() 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 9 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Load circuitry for switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aaf615 VCC VI VO DUT CL RT RL PULSE GENERATOR Table 9. Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC ≤ 2.5 ns 50 pF 500 Ω 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω |
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