74LVC595A_1

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 01 — 29 May 2007

11 of 19

NXP Semiconductors

74LVC595A

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 9.

The data set-up and hold times for the serial data input (DS)

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GND

GND

Q

7S output

SH

CP input

D

S input

Measurement points are given in Table 8.

Fig 10. The master reset (MR) to storage clock (STCP) set-up times

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MR input

STCP input

Qn outputs

GND

GND