ADC1010S datasheet(21/36 Pages) NXP

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ADC1010S_SER_1

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Preliminary data sheet

Rev. 01 — 9 April 2010

21 of 36

NXP Semiconductors

ADC1010S series

ADC1010S series; CMOS or LVDS DDR digital outputs

The output resistance is 50

Ω and is the combination of the an internal resistor and the

equivalent output resistance of the buffer. There is no need for an external damping

resistor. The drive strength of both data and DAV buffers can be programmed via the SPI

in order to adjust the rise and fall times of the output digital signals (see Table 30):

11.5.2 Digital output buffers: LVDS DDR mode

The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1

(see Table 23).

Each output should be terminated externally with a 100

Ω resistor (typical) at the receiver

side (Figure 22) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 23 and

Table 32).

The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via

the SPI (bits DAVI[1:0] and DATA[1:0]; see Table 31) in order to adjust the output logic

voltage levels.

Fig 22. LVDS DDR digital output buffer - externally terminated

Fig 23. LVDS DDR digital output buffer - internally terminated

VCCO

3.5 mA

typ

DnP/Dn + 1P

DnM/Dn + 1M

OGND

100

−

005aaa058

−

RECEIVER

VCCO

OGND

005aaa059

DxP/Dx + 1P

DxM/Dx + 1M

100

3.5 mA

typ

−

RECEIVER

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