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CS8422 Datasheet(PDF) 81 Page - Cirrus Logic |
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CS8422 Datasheet(HTML) 81 Page - Cirrus Logic |
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81 / 82 page ![]() DS692F1 81 CS8422 18.REVISION HISTORY Release Changes PP1 Added interchannel phase deviation to Performance Specifications - Sample Rate Converter table Added gain error to Performance Specifications - Sample Rate Converter table Added 32 kHz:48 kHz dynamic range to Performance Specifications - Sample Rate Converter table Updated (Note 2) in Performance Specifications - Sample Rate Converter table Updated values in DC Electrical Characteristics table Changed (Note 3) and (Note 4) in DC Electrical Characteristics table Updated RMCK jitter specification in Switching Specifications table Changed (Note 9) in Switching Specifications table Moved SDIN/TDM_IN setup and hold times in Switching Specifications table Changed master mode non-TDM I/OSCLK minimum frequency in Switching Specifications table Changed tsrs value in Switching Characteristics - Control Port - SPI mode Changed tirs value in Switching Characteristics - Control Port - I²C mode Fixed calculation error in Section 5.1.5.2 TDM Slave Mode Added note to Section 11.9 Recovered Master Clock Ratio Control & Misc. (09h) Added Section 12.6 Jitter Tolerance Added Section 13. Performance Plots Added Section 17. References Updated VIH minimum specification in Digital Interface Specifications table Updated VIL maximum specification in Digital Interface Specifications table Updated Input Hysteresis specification in Digital Interface Specifications table Added (Note 6) to Digital Interface Specifications table Removed VIH maximum specification in Digital Interface Specifications table Removed VIL minimum specification in Digital Interface Specifications table PP2 Updated package dimensions in Section 14. Package Dimensions F1 Final Release Changed VA, VREG, and VL = 5.0 V normal operation values in DC Electrical Characteristics table Updated Figure 37 with test data from CS8422 Updated Figure 90 Updated hardware mode NVERR and RERR descriptions in Section 6.6.2 Hardware Mode Control Updated values in Switching Specifications table Added TDM_IN pin not supported in master mode in Switching Specifications table and Section 5.1.5.1 Updated Section 11.19 Receiver Error (13h) description |
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