ADS5484 datasheet(7/37 Pages) TI

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N+1

N+2

N+6

CLKH

CLKL

N+3

N+4

N+5

DRY

DATA

Sample

T0158-02

Latency = 5 Clock Cycles

Dx_y_P

Dx_y_M

CLKM

CLKP

DRY_M

DRY_P

Sampling

Clock Input

Data Clock

Output

Output Data

N – 1

E = Even Bits = B0, B2, B4, B6, B8, B10, B12, B14

O = Odd Bits = B1, B3, B5, B7, B9, B11, B13, B15

Dx_y_P/M are LVDS outputs that have two bits per pair (EVEN and ODD). The values for x and y are 0_1, 2_3, 4_5, ... 14_15.

Aperture

Delay

ADS5484

ADS5485

www.ti.com ............................................................................................................................................... SLAS610C – AUGUST 2008 – REVISED OCTOBER 2009

TIMING INFORMATION

Figure 1. Timing Diagram

TIMING CHARACTERISTICS

(1)

Typical values at TA = 25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,

sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock,

unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

200

Aperture jitter, rms

Internal jitter of the ADC

Latency

cycles

tCLK

Clock period

1e9/CLK

100

CLK = max rated clock for that part

tCLKH

Clock pulse duration, high

0.5e9/CLK

number

tCLKL

Clock pulse duration, low

0.5e9/CLK

tDRY

CLK to DRY delay time(2)

1500

1900

2300

Zero crossing, 5-pF parasitic to GND

tDATA

CLK to DATA delay time(2)

1400

1900

2400

tSKEW

DATA to DRY skew

tDATA – tDRY, 5-pF parasitic to GND

–500

500

tRISE

DRY/DATA rise time

500

5-pF parasitic to GND

tFALL

DRY/DATA fall time

500

(1)

Timing parameters are assured by design or characterization, but not production tested.

(2)

DRY and DATA are updated on the rising edge of CLK input. The latency must be added to tDATA to determine the overall propagation

delay.

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ADS5484 Datasheet(PDF) 7 Page - Texas Instruments

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