MCP4821 datasheet(25/48 Pages) MICROCHIP

25 / 48 page

 2010 Microchip Technology Inc.

DS22244B-page 25

MCP4801/4811/4821

6.0

TYPICAL APPLICATIONS

The MCP4801/4811/4821 family of devices are general

purpose, single channel voltage output DACs for

various applications where a precision operation with

low-power and internal voltage reference is required.

Applications generally suited for the devices are:

• Set Point or Offset Trimming

• Sensor Calibration

• Precision Selectable Voltage Reference

• Portable Instrumentation (Battery-Powered)

• Calibration of Optical Communication Devices

6.1

Digital Interface

The MCP4801/4811/4821 devices utilize a 3-wire

synchronous serial protocol to transfer the DAC’s setup

and input codes from the digital devices. The serial

protocol can be interfaced to SPI or Microwire

peripherals which are common on many microcon-

troller units (MCUs), including Microchip’s PIC® MCUs

and dsPIC® DSCs.

In addition to the three serial connections (CS, SCK

and SDI), the LDAC signal synchronizes the DAC

output with LDAC pin event. By bringing the LDAC pin

down “low”, the DAC input codes and settings in the

DAC input register are latched into the output register,

and the DAC analog output is updated. Figure 6-1

shows an example of the pin connections. Note that the

LDAC pin can be tied low (VSS) to reduce the required

connections from 4 to 3 I/O pins. In this case, the DAC

output can be immediately updated when a valid

16 clock transmission has been received and the CS

pin has been raised.

6.2

Power Supply Considerations

The typical application will require a bypass capacitor

to filter out noise in the power supply traces. The noise

can be induced onto the power supply’s traces from

various events such as digital switching or as a result

of changes on the DAC’s output. The bypass capacitor

helps minimize the effect of these noise sources.

Figure 6-1 illustrates an appropriate bypass strategy. In

this example, two bypass capacitors are used in paral-

lel: (a) 0.1 µF (ceramic) and (b)10 µF (tantalum). These

capacitors should be placed as close to the device

power pin (VDD) as possible (within 4 mm).

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, VDD and

VSS of the device should reside on the analog plane.

6.3

Output Noise Considerations

The voltage noise density (in µV/

Hz) is illustrated in

Figure 2-13. This noise appears at VOUT, and is

primarily a result of the internal reference voltage.

Its 1/f corner (fCORNER) is approximately 400 Hz.

Figure 2-14 illustrates the voltage noise (in mVRMS or

mVP-P). A small bypass capacitor on VOUT is an

effective method to produce a single-pole Low-Pass

Filter (LPF) that will reduce this noise. For instance, a

bypass capacitor sized to produce a 1 kHz LPF would

result in an ENREF of about 100 µVRMS. This would be

necessary when trying to achieve the low DNL error

performance (at G = 1x) that the MCP4801/4811/4821

devices are capable of. The tested range for stability

is .001 µF through 4.7 µF.

FIGURE 6-1:

Typical Connection

Diagram.

6.4

Layout Considerations

Inductively-coupled AC transients and digital switching

noises can degrade the output signal integrity, and

potentially reduce the device performance. Careful

board layout will minimize these effects and increase

the Signal-to-Noise Ratio (SNR). Bench testing has

shown

that

multi-layer

board

utilizing

low-inductance ground plane, isolated inputs and

isolated outputs with proper decoupling, is critical for

the best performance. Particularly harsh environments

may require shielding of critical signals.

Breadboards

and

wire-wrapped

boards

are

not

recommended if low noise is desired.

VDD

AVSS

VSS

VOUT

SDI

SDO

SCK

LDAC

CS0

1µF

C1 = 10 µF

C2 = 0.1 µF

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