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GTL2018 Datasheet(PDF) 3 Page - NXP Semiconductors |
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GTL2018 Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 14 page ![]() GTL2018_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 15 February 2007 3 of 14 NXP Semiconductors GTL2018 8-bit LVTTL to GTL transceiver 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 2. Pin configuration for TSSOP24 GTL2018PW GND VCC B0 A0 B1 A1 B2 A2 B3 A3 VREF GND GND A4 B4 A5 B5 A6 B6 A7 B7 VCC GND DIR 002aab604 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 Table 3. Pin description Symbol Pin Description GND 1, 7, 12, 19 ground (0 V) B0 2 data inputs/outputs (B side, GTL) B1 3 B2 4 B3 5 B4 8 B5 9 B6 10 B7 11 VREF 6 GTL reference voltage DIR 13 direction control input (LVTTL) VCC 14, 24 positive supply voltage A7 15 data inputs/outputs (A side, LVTTL) A6 16 A5 17 A4 18 A3 20 A2 21 A1 22 A0 23 |
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