LM75A_4

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 04 — 10 July 2007

5 of 24

NXP Semiconductors

LM75A

Digital temperature sensor and thermal watchdog

In both cases, comparator mode and interrupt mode, the OS output is activated only if a

number of consecutive faults, defined by the device fault queue, has been met. The fault

queue is programmable and stored in the two bits, B3 and B4, of the Configuration

register. Also, the OS output active state is selectable as HIGH or LOW by setting

accordingly the configuration register bit B2.

is set to 75

°C, the OS active state is selected LOW and the fault queue is equal to 1. The

temp reading data is not available until the first conversion is completed in about 100 ms.

The OS response to the temperature is illustrated in Figure 4.

device under the control of a controller or master device, using two device terminals, SCL

and SDA. The controller must provide the SCL clock signal and write/read data to/from the

Ω,

is needed for each of these two terminals. The bus communication protocols are

described in Section 7.10.

7.3 Slave address

device address pins A2, A1 and A0. Each of them is typically connected either to GND for

address. The other four MSB bits of the address data are preset to ‘1001’ by hard wiring

inside the LM75A. Table 4 shows the device’s complete address and indicates that up to

Fig 4.

OS response to temperature

002aad032

(1)

(1)

(1)

OS reset

OS active

OS reset

OS active

OS output in comparator mode

OS output in interrupt mode

reading temperature limits