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P89LPC913FDH Datasheet(PDF) 47 Page - NXP Semiconductors |
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P89LPC913FDH Datasheet(HTML) 47 Page - NXP Semiconductors |
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47 / 66 page ![]() P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 28 September 2007 47 of 66 NXP Semiconductors P89LPC912/913/914 8-bit microcontrollers with two-clock 80C51 core In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs. 8.25 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 23 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few µs to a few seconds. Please refer to the P89LPC912/913/914 User manual for more details. (1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence. Fig 23. Watchdog timer in Watchdog mode (WDTE = ‘1’) PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDCON (A7H) SHADOW REGISTER PRESCALER 002aaa905 8-BIT DOWN COUNTER WDL (C1H) watchdog oscillator PCLK ÷32 MOV WFEED1, #0A5H MOV WFEED2, #05AH reset(1) |
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