P89LPC9402 datasheet(35/60 Pages) NXP

35 / 60 page

P89LPC9402_1

Product data sheet

Rev. 01 — 22 April 2009

35 of 60

NXP Semiconductors

P89LPC9402

8-bit microcontroller with accelerated two-clock 80C51 core

7.23 Analog comparators

Two analog comparators are provided on the P89LPC9402. Input and output options allow

use of the comparators in a number of different conﬁgurations. Comparator operation is

such that the output is a logic 1 (which may be read in a register and/or routed to a pin)

when the positive input (one of two selectable pins) is greater than the negative input

(selectable from a pin or an internal reference voltage). Otherwise the output is a zero.

Each comparator may be conﬁgured to cause an interrupt when the output value changes.

The overall connections to both comparators are shown in Figure 15. The comparators

function to VDD = 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not

guaranteed to be stable for 10

µs. The corresponding comparator interrupt should not be

enabled during that time, and the comparator interrupt ﬂag must be cleared before the

interrupt is enabled in order to prevent an immediate interrupt service.

7.23.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to as

Vref(bg), is 1.23 V ± 10 %.

7.23.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is

set whenever the comparator output changes state. The ﬂag may be polled by software or

may be used to generate an interrupt. The two comparators use one common interrupt

vector. If both comparators enable interrupts, after entering the interrupt service routine,

the user needs to read the ﬂags to determine which comparator caused the interrupt.

7.23.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down mode.

Fig 15. Comparator input and output connections

comparator 1

CP1

CN1

(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

Vref(bg)

OE1

CO1

CMF1

interrupt

002aae456

CMP1 (P0.6)

CMF2

comparator 2

OE2

CO2

CMP2 (P0.0)

CP2

CN2

(P0.2) CIN2A

(P0.1) CIN2B

change detect

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