 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
P89LPC9402 Datasheet(PDF) 49 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P89LPC9402 Datasheet(HTML) 49 Page - NXP Semiconductors |
|
|
49 / 60 page  P89LPC9402_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 22 April 2009 49 of 60 NXP Semiconductors P89LPC9402 8-bit microcontroller with accelerated two-clock 80C51 core Table 14. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2] Symbol Parameter Conditions Variable clock fosc = 18 MHz Unit Min Max Min Max fosc(RC) internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz fosc(WD) internal watchdog oscillator frequency 320 520 320 520 kHz fosc oscillator frequency 0 18 - - MHz Tcy(clk) clock cycle time see Figure 18 55 - - - ns fCLKLP low-power select clock frequency 0 8 - - MHz Glitch filter tgr glitch rejection time P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST 125 - 125 - ns tsa signal acceptance time P1.5/RST pin - 15 - 15 ns any pin except P1.5/RST 50 - 50 - ns External clock tCHCX clock HIGH time see Figure 18 22 Tcy(clk) − tCLCX 22 - ns tCLCX clock LOW time see Figure 18 22 Tcy(clk) − tCHCX 22 - ns tCLCH clock rise time see Figure 18 -5 - 5 ns tCHCL clock fall time see Figure 18 -5 - 5 ns Shift register (UART mode 0) TXLXL serial port clock cycle time see Figure 17 16Tcy(clk) - 888 - ns tQVXH output data set-up to clock rising edge time see Figure 17 13Tcy(clk) - 722 - ns tXHQX output data hold after clock rising edge time see Figure 17 -Tcy(clk) + 20 - 75 ns tXHDX input data hold after clock rising edge time see Figure 17 -0 - 0 ns tXHDV input data valid to clock rising edge time see Figure 17 150 - 150 - ns SPI interface fSPI SPI operating frequency slave 0 CCLK ⁄6 0 3.0 MHz master - CCLK ⁄4 - 4.5 MHz TSPICYC SPI cycle time see Figure 19, 20, 21, 22 slave 6 ⁄CCLK - 333 - ns master 4 ⁄CCLK - 222 - ns tSPILEAD SPI enable lead time see Figure 21, 22 slave 250 - 250 - ns tSPILAG SPI enable lag time see Figure 21, 22 slave 250 - 250 - ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
