PCA2125TS datasheet(14/36 Pages) NXP

14 / 36 page

PCA2125_1

Product data sheet

Rev. 01 — 28 July 2008

14 of 36

NXP Semiconductors

PCA2125

SPI Real-time clock/calendar

The minute and second ﬂag (bit MSF) is set to logic 1 when either the seconds or the

minutes counter increments according to the currently enabled interrupt. The ﬂag can be

read and cleared by the interface. The status of bit MSF does not affect the INT pulse

generation. If the MSF ﬂag is not cleared prior to the next coming interrupt period, an INT

pulse will still be generated.

The purpose of the ﬂag is to allow the controlling system to interrogate the PCA2125 and

identify the source of the interrupt such as the minute/second or countdown timer.

a. INT and MSF when SI enabled (MSF ﬂag not cleared after an interrupt)

b. INT and MSF when only MI enabled

Bit TI_TP is set to logic 1 resulting in 1

⁄

64 Hz wide interrupt pulse.

Fig 9.

INT example for bits SI and MI

Table 26.

Effect of bits MI and SI on INT generation

Minute interrupt (bit MI)

Second interrupt (bit SI) Result

no interrupt generated

an interrupt once per minute

an interrupt once per second

001aai520

seconds counter

minutes counter

INT

MSF

001aai521

seconds counter

minutes counter

INT

MSF

PCA2125TS Datasheet(PDF) 14 Page - NXP Semiconductors