PCA9541ADSLASH03 datasheet(7/41 Pages) NXP

7 / 41 page

PCA9541A_3

Product data sheet

Rev. 03 — 16 July 2009

7 of 41

NXP Semiconductors

PCA9541A

2-to-1 I2C-bus master selector with interrupt logic and reset

Functional description

Refer to Figure 1 “Block diagram of PCA9541A”.

8.1 Device address

Following a START condition, the upstream master that wants to control the I2C-bus or

make a status check must send the address of the slave it is accessing. The slave

address of the PCA9541A is shown in Figure 5. To conserve power, no internal pull-up

resistors are incorporated on the hardware selectable pins and they must be pulled HIGH

or LOW.

The last bit of the slave address deﬁnes the operation to be performed. When set to

logic 1 a read is selected, while logic 0 selects a write operation.

Remark: Reserved I2C-bus addresses must be used with caution since they can interfere

with:

• ‘reserved for future use’ I2C-bus addresses (1111 1XX)

• slave devices that use the 10-bit addressing scheme (1111 0XX)

8.2 Command Code

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9541A, which will be stored in the Command Code register.

The 2 LSBs are used as a pointer to determine which register will be accessed.

If the auto-increment ﬂag is set (AI = 1), the two least signiﬁcant bits of the Command

Code are automatically incremented after a byte has been read or written. This allows the

user to program the registers sequentially or to read them sequentially.

• During a read operation, the contents of these bits will roll over to 00b after the last

allowed register is accessed (10b).

Fig 5.

Slave address

002aab390

A0 R/W

fixed

hardware

selectable

Fig 6.

Command Code

002aab391

auto-increment

PCA9541AD/03 Datasheet(PDF) 7 Page - NXP Semiconductors