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PCA9674ATS Datasheet(PDF) 6 Page - NXP Semiconductors

Part # PCA9674ATS
Description  Remote 8-bit I/O expander for Fm I2C-bus with interrupt
PDF  32 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9674ATS Datasheet(HTML) 6 Page - NXP Semiconductors

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PCA9674_PCA9674A_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 15 June 2009
6 of 32
NXP Semiconductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
[1]
HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7.
Functional description
Refer to Figure 1 “Block diagram of PCA9674/74A”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9674/74A is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of
64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 5 “PCA9674 address map” and Table 6 “PCA9674A address map”.
Remark: When using the PCA9674A, the General Call address (0000 0000b) and the
Device ID address (1111 100Xb) are reserved and cannot be used as device address.
Failure to follow this requirement will cause the PCA9674A not to acknowledge.
Remark: When using the PCA9674 or the PCA9674A, reserved I2C-bus addresses must
be used with caution since they can interfere with:
• “reserved for future use” I2C-bus addresses (0000 011, 1111 101, 1111 110,
1111 111)
• slave devices that use the 10-bit addressing scheme (1111 0xx)
• High speed mode (Hs-mode) master code (0000 1xx)
Table 4.
Pin description for HVQFN16
Symbol
Pin
Description
AD2
1
address input 2
P0
2
quasi-bidirectional I/O 0
P1
3
quasi-bidirectional I/O 1
P2
4
quasi-bidirectional I/O 2
P3
5
quasi-bidirectional I/O 3
VSS[1]
6
supply ground
P4
7
quasi-bidirectional I/O 4
P5
8
quasi-bidirectional I/O 5
P6
9
quasi-bidirectional I/O 6
P7
10
quasi-bidirectional I/O 7
INT
11
interrupt output (active LOW)
SCL
12
serial clock line
SDA
13
serial data line
VDD
14
supply voltage
AD0
15
address input 0
AD1
16
address input 1



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