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PSMN059-150Y Datasheet(PDF) 2 Page - NXP Semiconductors |
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PSMN059-150Y Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 12 page ![]() PSMN059_150Y_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 5 May 2008 2 of 12 NXP Semiconductors PSMN059-150Y N-channel TrenchMOS standard level FET 3. Ordering information 4. Limiting values Table 2. Ordering information Type number Package Name Description Version PSMN059-150Y LFPAK plastic single-ended surface-mounted package; 4 leads SOT669 Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ T j ≤ 150 °C - 150 V VDGR drain-gate voltage 25 °C ≤ T j ≤ 150 °C; RGS =20kΩ - 150 V VGS gate-source voltage - ±20 V ID drain current Tmb =25 °C; VGS = 10 V; see Figure 2 and 3 -43 A Tmb = 100 °C; VGS = 10 V; see Figure 2 - 27.7 A IDM peak drain current Tmb =25 °C; pulsed; tp ≤ 10 µs; see Figure 3 - 129 A Ptot total power dissipation Tmb =25 °C; see Figure 1 - 113 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Source-drain diode IS source current Tmb =25 °C - 52 A ISM peak source current Tmb =25 °C; pulsed; tp ≤ 10 µs - 208 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy unclamped inductive load; ID = 12.1 A; tp = 0.21 ms; VDS ≤ 150 V; RGS =50 Ω; VGS = 10 V; starting at Tj =25 °C - 255 mJ |
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