SC18IS600_601_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 28 July 2008

7 of 30

NXP Semiconductors

SC18IS600/601

6.2.1.1

Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to

reconfigure the pin. This is possible because when the pin outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a large current. There are three pull-up

transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the pin latch

for the pin contains a logic 1. This very weak pull-up sources a very small current that will

pull the pin HIGH if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the pin latch for the pin

contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the

primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is

pulled LOW by an external device, the weak pull-up turns off, and only the very weak

pull-up remains on. In order to pull the pin LOW under these conditions, the external

device has to sink enough current to overpower the weak pull-up and pull the pin below its

input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up

LOW-to-HIGH transitions on a quasi-bidirectional pin when the pin latch changes from a

logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two system clock

cycles quickly pulling the pin HIGH.

The quasi-bidirectional pin configuration is shown in Figure 6.

Although the SC18IS600/601 is a 3 V device, most of the pins are 5 V tolerant. If 5 V is

applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from

configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression

circuit.

Fig 6.

Quasi-bidirectional output configuration

002aab882

2 SYSTEM

CLOCK

CYCLES

weak

strong

very

weak

PP

P

pin latch data

GPIOn,

IOn pin

glitch rejection

input data