HT66F20 datasheet(137/250 Pages) HOLTEK

137 / 250 page

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60

HT66FU30/HT66FU40/HT66FU50/HT66FU60

Rev. 1.20

137

June 4, 2010

A/D Operation

The START bit in the ADCR0 register is used to start

and reset the A/D converter. When the microcontroller

sets this bit from low to high and then low again, an ana-

log to digital conversion cycle will be initiated. When the

START bit is brought from low to high but not low again,

the EOCB bit in the ADCR0 register will be set high and

the analog to digital converter will be reset. It is the

START bit that is used to control the overall start opera-

tion of the internal analog to digital converter.

The EOCB bit in the ADCR0 register is used to indicate

when the analog to digital conversion process is com-

plete. This bit will be automatically set to

²0² by the

microcontroller after a conversion cycle has ended. In

addition, the corresponding A/D interrupt request flag

will be set in the interrupt control register, and if the inter-

rupts are enabled, an appropriate internal interrupt sig-

nal will be generated. This A/D internal interrupt signal

will direct the program flow to the associated A/D inter-

nal interrupt address for processing. If the A/D internal

interrupt is disabled, the microcontroller can be used to

poll the EOCB bit in the ADCR0 register to check

whether it has been cleared as an alternative method of

detecting the end of an A/D conversion cycle.

The clock source for the A/D converter, which originates

from the system clock fSYS, can be chosen to be either

fSYS or a subdivided version of fSYS. The division ratio

value is determined by the ADCK2~ADCK0 bits in the

ADCR1 register.

Although the A/D clock source is determined by the sys-

tem clock fSYS, and by bits ADCK2~ADCK0, there are

some limitations on the maximum A/D clock source

speed that can be selected. As the minimum value of per-

missible A/D clock period, tADCK,is0.5

ms, care must be

taken for system clock frequencies equal to or greater

than 4MHz. For example, if the system clock operates at

a frequency of 4MHz, the ADCK2~ADCK0 bits should

not be set to

²000². Doing so will give A/D clock periods

that are less than the minimum A/D clock period which

may result in inaccurate A/D conversion values. Refer to

the following table for examples, where values marked

with an asterisk * show where, depending upon the de-

vice, special care must be taken, as the values may be

less than the specified minimum A/D Clock Period.

fSYS

A/D Clock Period (tADCK)

ADCK2,

ADCK1,

ADCK0

= 000

(fSYS)

ADCK2,

ADCK1,

ADCK0

= 001

(fSYS/2)

ADCK2,

ADCK1,

ADCK0

= 010

(fSYS/4)

ADCK2,

ADCK1,

ADCK0

=011

(fSYS/8)

ADCK2,

ADCK1,

ADCK0

= 100

(fSYS/16)

ADCK2,

ADCK1,

ADCK0

= 101

(fSYS/32)

ADCK2,

ADCK1,

ADCK0

=110

(fSYS/64)

ADCK2,

ADCK1,

ADCK0

= 111

1MHz

ms2ms4ms8ms16ms32ms64ms

Undefined

2MHz

500ns

ms2ms4ms8ms16ms32ms

Undefined

4MHz

250ns*

500ns

ms2ms4ms8ms16ms

Undefined

8MHz

125ns*

250ns*

500ns

ms2ms4ms8ms

Undefined

12MHz

83ns*

167ns*

333ns*

667ns

1.33

2.67

5.33

Undefined

A/D Clock Period Examples

Controlling the power on/off function of the A/D con-

verter circuitry is implemented using the ADOFF bit in

the ADCR0 register. This bit must be zero to power on

the A/D converter. When the ADOFF bit is cleared to

zero to power on the A/D converter internal circuitry a

certain delay, as indicated in the timing diagram, must

be allowed before an A/D conversion is initiated. Even if

no pins are selected for use as A/D inputs by clearing

the ACE11~ACE0 bits in the ACERH and ACERL regis-

ters, if the ADOFF bit is zero then some power will still

be consumed. In power conscious applications it is

therefore recommended that the ADOFF is set high to

reduce power consumption when the A/D converter

function is not being used.

The reference voltage supply to the A/D Converter can

be supplied from either the positive power supply pin,

VDD, or from an external reference sources supplied on

pin VREF. The desired selection is made using the

VREFS bit. As the VREF pin is pin-shared with other

functions, when the VREFS bit is set high, the VREF pin

function will be selected and the other pin functions will

be disabled automatically.

A/D Input Pins

All of the A/D analog input pins are pin-shared with the

I/O pins on Port A, PE6, PF7, PF0 or PF1 as well as

other functions. The ACE11~ ACE0 bits in the ACERH

and ACERL registers, determine whether the input pins

are setup as A/D converter analog inputs or whether

they have other functions. If the ACE11~ ACE0 bits for

its corresponding pin is set high then the pin will be

setup to be an A/D converter input and the original pin

functions disabled. In this way, pins can be changed un-

der program control to change their function between

A/D inputs and other functions. All pull-high resistors,

which are setup through register programming, will be

automatically disconnected if the pins are setup as A/D

inputs. Note that it is not necessary to first setup the A/D

HT66F20 Datasheet(PDF) 137 Page - Holtek Semiconductor Inc

HT66F20 Datasheet(HTML) 137 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL