HT66F20 datasheet(138/250 Pages) HOLTEK

138 / 250 page

HT66F20/HT66F30/HT66F40/HT66F50/HT66F60

HT66FU30/HT66FU40/HT66FU50/HT66FU60

Rev. 1.20

138

June 4, 2010

pin as an input in the PAC, PEC or PFC port control reg-

ister to enable the A/D input as when the ACE11~ ACE0

bits enable an A/D input, the status of the port control

The A/D converter has its own reference voltage pin,

VREF, however the reference voltage can also be sup-

plied from the power supply pin, a choice which is made

through the VREFS bit in the ADCR1 register. The ana-

log input values must not be allowed to exceed the value

of VREF.

Summary of A/D Conversion Steps

The following summarises the individual steps that

should be executed in order to implement an A/D con-

version process.

· Step 1

Select the required A/D conversion clock by correctly

programming bits ADCK2~ADCK0 in the ADCR1 reg-

ister.

· Step 2

Enable the A/D by clearing the ADOFF bit in the

ADCR0 register to zero.

· Step 3

Select which channel is to be connected to the internal

A/D converter by correctly programming the

ACS4~ACS0 bits which are also contained in the

ADCR1 and ADCR0 register.

· Step 4

Select which pins are to be used as A/D inputs and

configure them by correctly programming the

ACE11~ACE0 bits in the ACERH and ACERL

registers.

· Step 5

If the interrupts are to be used, the interrupt control

registers must be correctly configured to ensure the

A/D converter interrupt function is active. The master

interrupt control bit, EMI, and the A/D converter inter-

rupt bit, EADI, must both be set high to do this.

· Step 6

The analog to digital conversion process can now be

initialised by setting the START bit in the ADCR regis-

ter from low to high and then low again. Note that this

bit should have been originally cleared to zero.

· Step 7

To check when the analog to digital conversion pro-

cess is complete, the EOCB bit in the ADCR0 register

can be polled. The conversion process is complete

when this bit goes low. When this occurs the A/D data

registers ADRL and ADRH can be read to obtain the

conversion value. As an alternative method, if the in-

terrupts are enabled and the stack is not full, the pro-

gram can wait for an A/D interrupt to occur.

Note: When checking for the end of the conversion

process, if the method of polling the EOCB bit in the

ADCR0 register is used, the interrupt enable step

above can be omitted.

t A D C

A / D c o n v e r s i o n t i m e

0 0 0 1 1 B

0 0 0 1 0 B

S T A R T

E O C B

A C S 4 ~ A C S 0

P o w e r - o n

R e s e t

E n d o f A / D

c o n v e r s i o n

1 : D e f i n e p o r t c o n f i g u r a t i o n

2 : S e l e c t a n a l o g c h a n n e l

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

A / D s a m p l i n g t i m e

t A D S

0 0 0 0 0 B

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

0 0 0 0 1 B

S t a r t o f A / D

c o n v e r s i o n

R e s e t A / D

c o n v e r t e r

E n d o f A / D

c o n v e r s i o n

A / D s a m p l i n g t i m e

t A D S

o f f

o n

t O N 2 S T

t A D C

A / D c o n v e r s i o n t i m e

o f f

A D O F F

A D C M o d u l e

O N

A/D Conversion Timing

P A 0 / A N 0

P F 1 / A N 1 1

1 . 2 5 V

V 1 2 5 E N

B u f f e r

P B 5 / V R E F

V D D

V R E F S

V R E F

1 2 - b i t A D C

B a n d g a p

R e f e r e n c e

V o l t a g e

I n p u t V o l t a g e

A C S 4 ~ A C S 0

A/D Input Structure

HT66F20 Datasheet(PDF) 138 Page - Holtek Semiconductor Inc

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